# How does USB superspeed electrical signaling work?

I've been reading a bunch, including the USB 3.0 spec, and I still don't get it. The transmit data lines are both capacitively coupled, so at the connector, SSTX are 0 V average?

Yet the voltage level diagram shows single-ended signals with a 0.3 VDC bias, is this before or after the coupling caps?:

Wouldn't this produce negative voltages on the receiver? Aren't the receiver ICs single supply? Is there a DC bias on either input or output? I read the part about how "8b/10b coding is DC-free", but I don't think that matters; it's like sending a 50% duty cycle square wave?

This is the closest I can find to an equivalent circuit (for a TI redriver):

• USB 1/2 is I believe terminated with a resistor network that biases it to ground. There must be termination resistors somewhere not shown. Commented Nov 18, 2014 at 23:39
• pjc50, Superspeed USB 3 does not use the timerination and singalling of USB 1 & 2. It uses four additional conductors not present in USB 1 & 2. The termination is present in the USB 3 transceiver chips, and should not have a DC bias. Commented Nov 19, 2014 at 2:53

In the example waveforms you show, the voltages are at the pins of the chip, before the capacitive coupling. The transmitter has approximately 0.3V of DC bias because it runs on a positive voltage supply only. If the receiver was not connected, and you instead put a terminating resistor across the pair, you would find the average DC bias (after the capacitors) to be zero. With the receiver connected, you will find that the receiver is actually adding a DC bias to the signal, that DC bias being close to its transition threshold.

• "the receiver is actually adding a DC bias to the signal" How? How much? Commented Nov 19, 2014 at 3:18
• The "how" is some combimation of leakage or a deliberately introduced bias, or diode clamps. The amount depends on the receiver chip, and probably isn't specified. I would expect anywhere between 0.3 and 1.0V. Commented Nov 19, 2014 at 6:41

The input circuits are probably biased at either PECL logic levels or midrail. This is easily done when the input is capacitively coupled because the capacitor represents a massive impedance at low frequencies.

This requires that the data transmitted is dc balanced data i.e. contains no long-term dc values - this is achieved by either manchester encoding or scrambling. This works either on a balanced line or unbalanced line.

Some single supply inputs can of course work with negative voltages; consider the simple inverting op-amp input with unity gain on a single rail. If the inverting input is -3V the output will be forced to +3V with nothing anaomalous about either inputs at all. OK not all op-amps will work down to ground and this is a requirement for this type of circuit BUT it will still handle negative voltages on the input resistor without batting an eyelid.

• Ok but is this what's actually being done in USB 3.0? I know it uses DC-free 8b/10b encoding, for instance. Commented Nov 18, 2014 at 22:30
• Actually it is extremely uncommon for inputs to tolerate voltages below the lowest supply rail by more than a diode drop. For a differential receiver, the common-mode range is usually <= to the supply range, and the differential range <= twice the coomon Commented Nov 19, 2014 at 6:45
• Should have said "somewhat uncommon", since many RS-422 and RS-485 receivers do it. Anyhow, got cut off in writing my comment. ... and the differential range <= +/- the common mode range, often much less. The limited common mode range is one reason that the receivers are designed to introduce a DC bias, to keep an otherwise floating input within the common mode range. This depends on the use of capacitor or transformer isolation at the transmitter, receiver, or both. Commented Nov 19, 2014 at 10:35
• @EricSmith USB 3.0 has capacitor isolation at the transmitter only Commented Nov 19, 2014 at 15:24
• I realize that. I was referring to differential signalling over cable in general, as some standards work differently. Commented Nov 19, 2014 at 21:55