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I'm using a TPS54386 and currently designing a PCB layout. The data sheet says to avoid via's within a certain loop; I was wondering what would happen or if anything would if I went ahead and placed via's anyway to save space.

enter image description here

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  • \$\begingroup\$ Is this something you plan to build and sell, or some little pet project? \$\endgroup\$
    – Matt Young
    Nov 19 '14 at 19:30
  • \$\begingroup\$ Not currently, but down the road maybe. \$\endgroup\$
    – Sam W
    Nov 19 '14 at 19:35
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You should look at the example design layout on page 31 and 32 of the datasheet, and be informed by it. Look how tight the layout is.

Yes, they did put vias in the output power loop, but not really in any of the power switching signals. In fact the vias all go to ground or return. No switching voltages involved.

Via structure used is 8 parallel vias per via section. Since the vias are in parallel they present very low inductance. For example, vias typically have 2nH or 3nH of inductance, so with 8 in parallel any added circuit inductance will be negligible. This means that the characteristics of the output capacitor C17 won't be changed and will have no impact on loop stability.

These vias only augment the return path in the output circuit by allowing return routing on the bottom layer. That bottom layer copper provides a low inductance (small loop area) path for the power switching of SW1, D2, and L2. If you want to add vias like that, you should have no problem.

If you want to add vias to the power switching routes that connect SW1 to D2 and L2 there could be trouble. Added inductance, especially between SW1 and D2, will make snubbing more difficult and increase noise.

Also, in your schematic, L1 and L2 are not the same. Is this intentional? The combination of L1 (47uH) and C13 (100uF) with \$f_o\$ of 2300Hz isn't a good match to the built-in compensation of the TPS54386 which has zeros a ~3300Hz.

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The short answer is, as long as your components are spec'd properly, it will probably work just fine. However, if you ever want to sell the circuit, you're going to need to do some compliance testing.

A 600kHz switching regulator with a poor layout will give you lots of radiated emissions problems when it comes EMC test time, especially in the AM band. The key to limiting the radiated emissions is minimize the switching current loop area. In a buck regulator, that is through the switch, inductor, and output cap. You can make that loop smaller, and control it better if it all remains on a single layer.

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It says in the design notes: -

Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor and rectifier diode. Avoid using vias in this loop.

However, in the PCB layout they defy their own instructions: -

enter image description here

Both C17 and D2 utilize vias in order to make connections in the PCB layout above and, they made an error in the PCB layout that I fixed (they had C17 disconnected from L2). So how do you rationalize this?

Picture errors on the layout are easy to see and correct but when it comes to vias they have used many parallel vias to overcome any hot-spot problems caused by single vias.

To see the error open the data sheet and look at the PCB guidelines: -

enter image description here

That's the simple truth of the matter.

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