Why not use audio codec chip as measurement ADC/DAC?

Question

I am working on a project that needs simultaneous ADC/DAC. The specs of the on-board ADC in typical microcontrollers are pretty weak, and separate ADC with good specs are much more expensive than audio codecs. For example, compare these three options:

(A) STM32F373 has three 16-bit, 50ksps max ADCs which reach just under 15 bits effective. This is maybe the best from ST for high resolution ADC; it also has some high-speed 12-bit ADCs and some DACs. Price: $3.26.

(B) an I2S-based audio codec, the PCM3168A has six 24-bit, 96ksps ADCs with 17.5 effective bits (if my reading of the datasheet is correct). This also has eight DACs with similar specs. All inputs/outputs are fully differential, and the highpass filter on the ADC can be turned off. Price: $4.90.

(C) the least expensive TI ADC with similar specs is the ADS1271, a 24-bit, 105ksps ADC with also ~17.5 effective bits. However, this is a $6.31 part, and has only one channel! A four-channel part goes for $14.65.

Thus, using audio codecs for measurement seems rather attractive.

Why not do this? Are there any unexpected drawbacks to using audio codecs for measurement?

Answer 1

Audio codecs are very linear and very low noise, but they are usually AC-coupled to eliminate DC offsets, and their absolute accuracy (scale factor) is not very tightly controlled, since these aspects are not as important in audio work. This makes them less suitable for general ADC/DAC applications.

Answer 2

The problem can be rephrased as: is it possible to apply parts with poor gain and offset stability in applications that demand the opposite. The answer is a resounding yes, with a bit of ingenuity.

I present the general concept below. It of course requires a lot of engineering over what's mentioned - the circuits are only meant to illustrate the operating principle. The choice of calibration algorithms, reference converters, switches and analog buffering and signal processing will determine the performance of the design.

DAC

The general requirement is to have one extra DAC channel more than n, the number output channels. A reference ADC is also required. Each output channel can be taken from one of two adjacent DACs. The ADC is fed output from one of the DACs. While n DACs feed the outputs, one is feeding the ADC and undergoes calibration. Once calibration is done, the DAC is returned to its output duty, and the next DAC is attached to the ADC.

^{simulate this circuit – Schematic created using CircuitLab}

The example above shows a 4CH DAC used to obtain 3 outputs. The switch positions are as below:

• CH1 calibrate, CH2-4 output: SW1 closed, SW11 down, SW12 down, SW13 down.

• CH2 calibrate, CH1,3-4 output: SW2 closed, SW11 up, SW12 down, SW13 down.

• CH3 calibrate, CH1-2,4 output: SW3 closed, SW11 up, SW12 up, SW13 down.

• (shown) CH4 calibrate, CH1-3 output: SW4 closed, SW11 up, SW12 up, SW13 up.

A test waveform is applied to the channel under calibration, and captured using a "decent" ADC. There are plenty of affordable, DC-accurate ADCs, even sigma-delta ones. The captured waveform can be measured to derive calibration coefficients - at the very least the offset and gain. The calibration itself is done digitally on the binary data fed into the DACs.

For minimal switching glitch feedthrough, the output selector switches can be optically actuated MOSFETs. Each of the pair of single-pole switches comprising a pair SW1x can be phased to operate with overlap. When both poles of SW1x are connected to the output, the output is effectively an average. For a little bit you need to feed two channels the same output data. Do note that each channel has a different calibration, so feeding same output to two channel DACs requires feeding different binary inputs.

This concept, when properly developed, can be used to produce very accurate, high-performance outputs at a very reasonable cost. If you're careful, you can get 16+ bit accurate channels for a couple dollars. Since most audio DACs produce small amplitude signals, one needs signal scaling and amplification. Any signal processing stages should be within the calibration loop, unless they are sufficiently DC-accurate. This concept also inherently ensures diagnostics of each channel.

ADC

The same approach can be applied in reverse: have one extra ADC channel, and a reference DAC. The input to each ADC can be taken from three sources: either one of two adjacent input channels, or the reference DAC. While n ADCs sample the inputs, one is sampling a reference signal from the DAC and undergoes calibration. Once calibration is done, the ADC is returned to its input duty, and the next ADC is attached to the DAC.

^{simulate this circuit}

The example above shows a 4CH ADC used to sample 3 inputs. The switch positions are as below:

• CH1 calibrate, CH2-4 input: SW1 closed, SW11 down, SW12 down, SW13 down.

• CH2 calibrate, CH1,3-4 input: SW2 closed, SW11 up, SW12 down, SW13 down.

• CH3 calibrate, CH1-2,4 input: SW3 closed, SW11 up, SW12 up, SW13 down.

• (shown) CH4 calibrate, CH1-3 input: SW4 closed, SW11 up, SW12 up, SW13 up.

Multi-Level Designs

It is possible to apply the same concept to the reference converter. Suppose you have a 6 channel audio codec, with 6 inputs and 6 outputs. You can apply it to a 4 channel analog I/O design, leaving 5 DACs for outputs, and one DAC for secondary reference, 5 ADC for inputs, one ADC for secondary reference. Finally, you need just one primary reference ADC or DAC. That one can be used to calibrate the secondary reference, that one can be used to calibrate the other secondary reference, and finally the secondary references are used to calibrate the ADCs and DACs used for I/O data conversion. It's pretty much a standards lab in miniature :)