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So I have PWM signal controlling an N-FET switch at around 20kHz.

While it works in theory, in reality it takes longer to switch the MOSFET off. I assume it is because of output capacity parameter?

And then there's the fact that it starts shutting off from negative voltage. Why is that?

Real world example uses BS170.

Blue trace - Vgs, Green trace - Vd:

Fantasies

Yellow trace - Vgs, Red trace - Vd:

IRL

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  • \$\begingroup\$ Is the yellow trace \$V_{GS}\$? What's the red trace? \$\endgroup\$ – diverger Nov 20 '14 at 12:31
  • \$\begingroup\$ Please explain which traces correspond to which measurement. Also, your simulation trace does not look like the input waveform is the same as the measurement (or the SPICE source) as there seems to be a a relatively slow rise and fall time. \$\endgroup\$ – Spehro Pefhany Nov 20 '14 at 12:35
  • \$\begingroup\$ @diverger Yeah, sorry, added trace descriptions. \$\endgroup\$ – andrey Nov 20 '14 at 12:39
  • \$\begingroup\$ "Red trace - Vgs, Yellow trace - Vd",are you sure? \$\endgroup\$ – diverger Nov 20 '14 at 12:47
  • \$\begingroup\$ @diverger Right, it's the other way around. \$\endgroup\$ – andrey Nov 20 '14 at 12:50
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The negative and positive overshoots you see in the actual waveform are probably resulting from how you have the circuit wired up. If you have long jumper wires and a poor grounding system this can lead to that behavior.

As far as to why the output rise time is so much slower than in reality than in the simulation - this is mostly due to the capacitance of the drain node in the circuit. This capacitance comes in part from the components themselves but may also be largely attributed to the way the circuit is built. For example if you have long leads and are using a pluggable type proto-board you will have more capacitance than if you built the circuit onto a real circuit board.

One way to evaluate just how much capacitance may exist on the drain node of your circuit is to go back to your simulation and add a capacitor from the drain to GND. Then iteratively adjust the capacitor value and rerun the simulation till the waveform starts to look much more similar to what you measured in the actual circuit.

You can substantially reduce the effect of the drain node capacitance by lowering the 200K / 100K resistors in your voltage divider to say 20K / 10K or even 2K / 1K.

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From BS170's datasheet, it shows

\$C_{OSS}= 30pF (max.) @V_{DS}=10V,V_{GS}=0V \$

At low \$V_{DS}\$, this capacitor will be larger, from you measurement, the rising time is about 30us, so the time constant should about 10us, your source's output impedance is about 70K ohms, so the average \$C_{OSS}\$ should be about 150pF. You can use this parameter to estimate your \$R_{2},R_{3}\$'s value.

From your measurement, both \$V_{GS}\$ and \$V_{D}\$ have a negative overshoot with similar amplitude, so, this may be caused by your circuit's ground layout, or the ground clamp position when you measuring.

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