My programmable power supply project in progressing slowly and now it's time to do something with overshooting of linear "postregulator" during power off and power on. Overshooting on step response is still waiting in the queue to be observed and corrected. Here is the latest schematics (right click to enlarge) this time with voltage control loop depicted (version with current control loop is discussed here).
Notice that switching preregulator (based on LM5118) is now up and running with functional tracking and it seems that it prevents power down/up overshooting but my intention is to add possibility to bypass it (using power mosfet or relay) to provide "pure linear mode of operation". Of course, in this mode max. power dissipation of Q1 will be limited to 30W. Overshooting is inherent for presented solution since before control loop is established (power on) or lost (power off) Q1 will conduct and deliver full input voltage (from C1-C3) to the output terminal. Obvious choice will be to build everything around P-ch mosfet, but it seems that is easier to find N-ch which can deliver continuously 3-5A up to 60V.
The question is: it it possible to somehow avoid mentioned overshooting and still use N-channel mosfet as serial regulator?
Maybe it make sense to add schematic of currently used bias power supply. It's rather simple supplied with aux transformer and common ground is connected to common ground of main power supply (It the future I'd like to derive bias power from main DCin with step-down and inverting circuits).
Now with DSO in place I can add some real measurements. First picture shown what is happened without any modification and no load connected. Bias supply is evidently slow and it possibly participate greatly in 110ms overshoot during power up.
Situation with load of 1A on power up does not improve situation a lot (overshoot is still 66ms long and undershoot is also exists), since bias supply comes too late.
Now with adding Rff (50K) and without removing ZD2 (emitter is still on approx. -6V) we have the following situation:
Power up overshoot is shorter, but Vout ends up to -4.4V and no regulation is possible. If I disconnect emitter of Q3 from ZD2 and connect it to the GND I got the following situation:
Vout is now 1.28V and again without possibility to change its value. Measuring the Vbe of Q3 it's clear that when proper IC1 bias supply is not present that Vbe instantly drop down to zero (or lets say well below 0.6-0.7V). Therefore it seems that adding anything after the IC1A will not improve situation. I also made one additional test: Q1 drain was connected to +15V from bias power supply. In that case and without any load on power up we have the following situation:
Some oscillations exists but it looks much lower then before and I believe that it now belongs to improper compensation of voltage control loop. If something should not be present during the power up is the output of IC1A to Q3. If analog switch (such as CD4066, ADG1436, etc.) has to be used then it should be deploy to connect and disconnect Q3 base in the right moment.
My plan for the moment is to derive bias power supply for main supply (use buck SMPS to step down from 50VDC to +15V with inverter to get -15V). Another possibility is to use "Power good" signal from SMPS used for bias power to connect/disconnect IC1Aout to Q3B. Does that make any sense?
EDIT (2014-12-03) Part 2:
Gsills propose one important improvement that seems that can make a real change. Adding diode in parallel with integrator capacitor will remove ringing. Here is the picture with the same setup as the latest from previous edit (main and bias supply is the same):
Note that this works only with Q3 emitter connected to ground not below it. The question is this case is: does diode could remain connected or it has to be disconnected shortly after the power up?
I'm adding power up oscillogram with the following signals: CH2:Vin (32VDC), CH1:Vout (5V), CH3:+Vbias (+15V) and CH4:-Vbias (-15V). It's clear that overshoot is happening while working bias supply is still not established.
I'm still thinking that maybe control of Q1 bias could be a solution for both power up and power down issue. Idea is to get "power good" signal derived from other logic to control some sort of switch that will connect or disconnect bias resistor to Q1 gate. If this makes sense question is what component to use as a switch device: low power BJT or MOSFET? (relay even a small one I think is not a solution).