Power supply overshooting during power up and power down

Question

My programmable power supply project in progressing slowly and now it's time to do something with overshooting of linear "postregulator" during power off and power on. Overshooting on step response is still waiting in the queue to be observed and corrected. Here is the latest schematics (right click to enlarge) this time with voltage control loop depicted (version with current control loop is discussed here).

Notice that switching preregulator (based on LM5118) is now up and running with functional tracking and it seems that it prevents power down/up overshooting but my intention is to add possibility to bypass it (using power mosfet or relay) to provide "pure linear mode of operation". Of course, in this mode max. power dissipation of Q1 will be limited to 30W. Overshooting is inherent for presented solution since before control loop is established (power on) or lost (power off) Q1 will conduct and deliver full input voltage (from C1-C3) to the output terminal. Obvious choice will be to build everything around P-ch mosfet, but it seems that is easier to find N-ch which can deliver continuously 3-5A up to 60V.

The question is: it it possible to somehow avoid mentioned overshooting and still use N-channel mosfet as serial regulator?

EDIT (2014-11-23):

Maybe it make sense to add schematic of currently used bias power supply. It's rather simple supplied with aux transformer and common ground is connected to common ground of main power supply (It the future I'd like to derive bias power from main DCin with step-down and inverting circuits).

EDIT (2014-12-03):

Now with DSO in place I can add some real measurements. First picture shown what is happened without any modification and no load connected. Bias supply is evidently slow and it possibly participate greatly in 110ms overshoot during power up.

Situation with load of 1A on power up does not improve situation a lot (overshoot is still 66ms long and undershoot is also exists), since bias supply comes too late.

Now with adding Rff (50K) and without removing ZD2 (emitter is still on approx. -6V) we have the following situation:

Power up overshoot is shorter, but Vout ends up to -4.4V and no regulation is possible. If I disconnect emitter of Q3 from ZD2 and connect it to the GND I got the following situation:

Vout is now 1.28V and again without possibility to change its value. Measuring the Vbe of Q3 it's clear that when proper IC1 bias supply is not present that Vbe instantly drop down to zero (or lets say well below 0.6-0.7V). Therefore it seems that adding anything after the IC1A will not improve situation. I also made one additional test: Q1 drain was connected to +15V from bias power supply. In that case and without any load on power up we have the following situation:

Some oscillations exists but it looks much lower then before and I believe that it now belongs to improper compensation of voltage control loop. If something should not be present during the power up is the output of IC1A to Q3. If analog switch (such as CD4066, ADG1436, etc.) has to be used then it should be deploy to connect and disconnect Q3 base in the right moment.

My plan for the moment is to derive bias power supply for main supply (use buck SMPS to step down from 50VDC to +15V with inverter to get -15V). Another possibility is to use "Power good" signal from SMPS used for bias power to connect/disconnect IC1Aout to Q3B. Does that make any sense?

EDIT (2014-12-03) Part 2:

Gsills propose one important improvement that seems that can make a real change. Adding diode in parallel with integrator capacitor will remove ringing. Here is the picture with the same setup as the latest from previous edit (main and bias supply is the same):

Note that this works only with Q3 emitter connected to ground not below it. The question is this case is: does diode could remain connected or it has to be disconnected shortly after the power up?

EDIT (2014-12-10):

I'm adding power up oscillogram with the following signals: CH2:Vin (32VDC), CH1:Vout (5V), CH3:+Vbias (+15V) and CH4:-Vbias (-15V). It's clear that overshoot is happening while working bias supply is still not established.

EDIT (2014-12-19):

I'm still thinking that maybe control of Q1 bias could be a solution for both power up and power down issue. Idea is to get "power good" signal derived from other logic to control some sort of switch that will connect or disconnect bias resistor to Q1 gate. If this makes sense question is what component to use as a switch device: low power BJT or MOSFET? (relay even a small one I think is not a solution).

Answer 1

That there is no output start-up spike with the preregulator in place will be because the soft-start of the LM5118 adds tens of milliseconds to the time allowed for the bias to come up and actively control the gate of Q1. That's a pretty reasonable way to have a more controlled start. But let's set that aside to look at some of the other things that can happen during start up.

Start-up power sequencing is always a big concern with any power supply. Things can get quite involved, making sure that proper bias is present at the right time. Here are some common causes of overshoot on start up, in rough order of prevalence:

1. Integrator wind up. A precharge occurs on the integrator capacitor at start, causing a hard start.

2. Uncontrolled start of \$V_{\text{Ref}}\$. A unit step start of \$V_{\text{Ref}}\$ can cause an overshoot of output voltage.

3. Local bias voltage coming up late, or unbalanced start. Unbalanced start of bias can happen when there is bipolar bias voltage. Either the positive or negative output can come up first, in which case the output can rail.

4. Lack of termination at startup. If the output is unloaded at start, the output can overshoot and stay at an excessive level for an extended period.

All of these causes should be checked. Integrator wind up and controlled start of \$V_{\text{Ref}}\$ always have to be managed, and will get further attention here. Local bias sequencing and balance can take many forms and is hard to say much about specifically, but now that the local bias schematic has been added to the question, it is somewhat doubtful that any imbalance or delay would be severe enough to cause overshoot. Lack of termination is usually not a significant factor in a linear supply, but could make any existing overshoot more severe.

Integrator Wind Up

Without an active loop, such as under start up conditions, an integrator capacitor will always become excessively charged. High gain and any offset voltage or input bias currents of the OpAmp will combine to make this so. Then when the loop becomes active, the error amplifier is railed and the supply output overshoots. All practical integrator circuits used in power supplies have some means added to constrain charge up of the integrator capacitor. Quite common is placing a diode in parallel with the capacitor.

Here, \$D_{\text{Lim}}\$ is configured such that if the output of the amplifier should normally be higher than \$V_{\text{Ref}}\$, the amplifier will behave as an integrator. But, for output voltages lower than \$V_{\text{Ref}}\$ no excess charge up of \$C_9\$ will occur and the amplifier will only have unity gain. So, the amplifier can not end up railed to the negative bias voltage. No or minimal overshoot. In the case that amplifier output should be lower than \$V_{\text{Ref}}\$ during normal loop operation, \$D_{\text{Lim}}\$ connection can be reversed to prevent railing to the positive bias supply rail.

Sometimes using a diode is not restrictive enough, especially if \$V_{\text{Ref}}\$ is adjustable over a wide range. In this case a normally closed single pole single throw (NC SPST) analog switch can be used in place of \$D_{\text{Lim}}\$ to make the error amplifier have unity or some proportional gain during start up. At the proper time the analog switch is opened and the error amplifier becomes an integrator again. No overshoot.

Uncontrolled Start of \$V_{\text{Ref}}\$

An abrupt step in \$V_{\text{Ref}}\$ can cause overshoot or ringing at the output. Although this happens a lot at start up, it's not strictly a start up problem. A control loop with inadequate phase margin, anything less than about 68 degrees, will overshoot or ring with a step of \$V_{\text{Ref}}\$. Best way to handle this in general is to design the loop to have adequate phase margin. Best practice at start up is to initiate start with \$V_{\text{Ref}}\$ at zero setting and then ramp to the desired setting over a period of milliseconds.

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Note: Initially it appeared that overshoot cause could be delay of local bias. Here is a test to verify and a possible solution offered.

Since it is crucial with this power stage to have active pull-down on Q1-G to maintain control of Q1-S, a crude pre-bias could be applied to Q3-B. A 50kOhm resistor, here shown as \$R_{\text{ff}}\$, could be connected from Q3-B to Q1-D. When voltage appears at Q1-D, Q3 would be turned on actively pulling down Q1-G. To make this work, D6 and D7 would have to be turned around, anodes tied together and R8, and D7-C to IC1A-1, and D6-C to IC2A-1 to allow Q3-B to be pulled down during regulation. This might be the simplest thing to do.

When \$R_{\text{ff}}\$ is not present, ripple rejection of the stage, open loop with \$D_7\$ cathode pulled low, is zero dB.

With \$R_{\text{ff}}\$ in place ripple rejection improved to 20dB. 50kOhm was chosen on a wim, and no effort was made to find a better value.