I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To this end, I am systematically measuring the time delays through specific LEs and specific inputs to those LEs. I know I can constrain specific combinatorial functions through the Assignment Editor, but is there a way to constrain which input is used? Right now my work flow sucks: change constraints in Assignment editor, hit compile, use the Engineering Change Order in the Chip planner to change all the LUT masks and inputs, hit check and compile, and then upload. Is there a way to get rid of the second compile, so that the first compile does what I want it to?

(For those that are wondering why I'm bothering: my circuit is unclocked and sensitive to the specific time delays of the LEs used. This is a non-linear dynamics/chaos theory research project, so the sensitivity is something I want. Thus, I need to know what values my experimental circuit takes in order to properly analyze it. If TimeQuest and/or ModelSim provide that information I would gladly avoid monotonous experiments and data collects, but I don't see how they could know anything about the manufacturing defects and silicon temperature and supply voltage etc.)


1 Answer 1


They cannot provide that information. The only information they have is 'best case' and 'worst case'. It is impossible to know how any individual chip will perform unless you go measure the specific chip you're interested in. The timing performance of the logic elements is only guaranteed to be somewhere within the 'best case' and 'worst case' over the specified voltage and temperature range. Parts that do not fall in this range are assigned a lower speed grade or discarded. If you get a different chip (even one from the same batch), the delays could vary all over the place within these bounds.

This is one of the main reasons fully asynchronous designs are not so nice to do on FPGAs - the performance could well vary between FPGAs enough to affect normal operation. Maybe it won't fail unless you get into a VT corner, but it's a risk. Generally the timing analysis really only works correctly for synchronous designs.

If your design is sensitive to the delays of the elements to this resolution, then there are two options: redesign it so it isn't, or build some sort of a self-calibration routine to calibrate out the delays. Naturally, the second option only works in very specific cases (e.g. CERN time-to-digital core). Otherwise, you're basically SOL.

  • \$\begingroup\$ This is a non-linear dynamics/chaos theory research problem, so the sensitivity is the point of the experiment (if that makes sense). \$\endgroup\$
    – Andrew
    Commented Nov 20, 2014 at 17:51
  • \$\begingroup\$ In that case, you're just going to have to do it manually. It might be a good idea to look in to some sort of scripted setup - generate a set of contstraints, build, program, measure, generate new constraints, rinse and repeat. Then get some coffee while it runs. I'm not sure if there is enough access to the constraints you're interested in from a script, but I would say it's worth looking at. \$\endgroup\$ Commented Nov 20, 2014 at 17:58
  • \$\begingroup\$ Do you mean the Tcl scripting that they mention? Any hints on where in the workflow I should insert (Analysis, fitting, compiling)? Thanks \$\endgroup\$
    – Andrew
    Commented Nov 20, 2014 at 19:34
  • \$\begingroup\$ That might be the only way to control the software to the granularity that you want. I am not familiar with the TCL workflow, unfortunately. Also, how are you making the delay measurements? Whatever scripting you do should ideally be able to take those measurements as well, if only to output a correlated log file. \$\endgroup\$ Commented Nov 20, 2014 at 19:45

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