# CCD Reset switch and sense capacitor

I'm trying to understand the circuit in figure 1 of this document which describes CCD interfacing (http://www.analog.com/library/analogdialogue/archives/32-1/signal_pro.html). Shown below:

My questions are, as follows:

Does this represent the circuit in the output stage of the CCD? Typically CS and the 2 MOSFETs would be internal to the CCD?

If I need to add these parts what value would I typically use for CS, which MOSFETs.

It is entirely possible to have a CCD detect single photons, so lets say you are imaging in a dim room and you have 2 electrons that have been generated. Lets say you need to generate 10 uV to get over the noise of the outside world. That means that your sense node should be $\dfrac{2*1.6e-19}{10e-6}= 32.2 aF$ i.e. $32.2*10^{-15}$ any stray capacitance in the outside world would swamp this. So even if your photodiodes could capture the photons and your transport register could move the charge to the output pin, you need to have the amplifier on chip.
So if you bias the amplifier correctly and generate the signals properly you should see that waveform come out of the pin. The $\delta V$ in the picture is the CDS value that you need. (Correlated Double sampling).
How the circuit works is very simple. the reset switch reset the sense node ($C_s$) to a known state. However, this generates a little uncertainly in that voltage (this is known as KTC noise). When the capacitor is floating, the horizontal shift register is actuated and charge is spilled onto the sense node, developing voltage which then controls the amplifier. $V =\dfrac{Q}{C}$ where Q = signal charge. If you take the difference between the reset state (with ktc noise) and the final state (when charge is on the node and it still has the ktc noise there) you get the signal voltage with teh ktc subtracted away.