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So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. No errors or warnings from the fpga tools. You go to lab and think, OH BOY, I'm going to program the FPGA and watch this work, but it doesn't. No data gets through, no signal move. Nothing. You check the power on the board and there is more than enough, even for the FPGA boot cycle. You check the routing on the PCB for critical signals, and they look good. What do you do next???

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    \$\begingroup\$ It's probably some simple error in how you're getting your bitfile into the FPGA. What FPGA specifically, and what tools are you using to load/debug it? \$\endgroup\$
    – Dave Tweed
    Nov 21 '14 at 16:15
  • \$\begingroup\$ Unit testing (should be done even before)? Trying to reduce the functionality until something starts to work? Or even try to program some very simple test design, just to check signals and the chip itself. \$\endgroup\$
    – Eugene Sh.
    Nov 21 '14 at 16:19
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    \$\begingroup\$ Can you load and run a different Bitfile? \$\endgroup\$
    – Botnic
    Nov 21 '14 at 16:32
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    \$\begingroup\$ Did you check your clock source? Is it running on the board? Maybe make a really simple design that just outputs 1/2 the clock on a pin. See if that works. Check your manual to see what pins you can check for feedback about loading. Altera has conf done, and an error pin, to let you know what happened not sure about Xilinx. \$\endgroup\$ Nov 21 '14 at 16:42
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    \$\begingroup\$ A good one that I've seen (cough done) is driven global reset from the wrong (inverted) logic level. Design loads, but does nothing... very frustrating. Easy to fix, but first you have to find it. \$\endgroup\$
    – markt
    Nov 22 '14 at 0:17
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As an answer to your question "What do you do next", here's some random things you should consider and measure:

Does it get programmed OK? Do you use some JTAG cable to connect to it? Does it identify itself correctly with the JTAG cable and programming software? Or do you use some EEPROM/FLASH to load the configuration at startup? Do you program the bitfile to the EEPROM/FLASH using the FPGA vendor's tools or with some other tools? Does the EEPROM/FLASH get programmed ok? Does the FPGA signal DONE after boot / after loading the configuration (Xilinx)? Does it use a reasonable amount of current? Does the current change when the configuration is loaded?

With all digital circuits, everything comes to three basics: Power, Clock and Reset. Try to confirm these, one by one. Try to generate and load a configuration that does very basic things, such as pulling some output high, another low. If you have some buttons/LEDs on board, try to route some button signal directly to a LED signal. Anything that doesn't require a clock. Then add a binary counter from the clock source to some outputs. Measure that you get some outputs toggling up/down with the clock.

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