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I have the following assignment for a project at college and I have a few questions regarding it.

You are to design a Mealy state diagram for a digital lock. Assume that two debounced push-buttons, A and B, are available to enter the combination. An electromechanical interlock guarantees that the buttons cannot be activated simultaneously. The lock should have the following features:

The combination is A-A-B-A-B-A. If this sequence is correctly entered, an output signal is asserted that causes the lock to open.

For any state, three B pulses in a row should guarantee to reset the control to its initial state.

When any out-of-sequence use of the A push-button occurs, an output is asserted that rings a bell to warn that the lock is being tampered with.

Once the lock is open, pressing either A or B will cause the lock to close without signaling an error. Draw a Mealy state diagram for this finite state machine. Indicate what each state represents and what input conditions cause state and output changes. Not everything may have been specified, so write down any assumptions you make.

I have to implement this using only MUX'es and JK flip-flops. My progress so far:

-I have 10 states the machine can be in:

S0 -> nothing happened yet

S1 -> input = A

S2 -> input = AA

S3 -> input = AAB

S4 -> input = AABA

S5 -> input = AABAB

S6 -> input = AABABA (the output should be 1 when we get to this state)

S7 -> input = B

S8 -> input = BB

S9 -> input = A(this would set off the alarm)

-I now have to use 4 JK flip-flops(since the states would be written as Q3,Q2,Q1,Q0) so I have a giant truth table for the current state(Q3,2,1,0), input(A and B), next state and each JK flip flop

-I then proceeded to draw Karnaugh diagrams for each of the J and K functions and minimize them as much as I can(but they are still really REALLY long).

Now the only thing left would be to make the circuit and this is the part where I'm stuck. Having so many variables (Q3,2,1,0, A and B) how should I start making the equivalent circuit? Any help would be greatly appreciated :)

EDIT2: removed a question

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  • \$\begingroup\$ This could be a related question. \$\endgroup\$ – K. Rmth Jul 7 '15 at 11:12
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No, an XOR gate will not help. In this type of state diagram, it's implicit that in any state, there are three possible inputs: no button, button A or button B. When there's no button press, you always stay in the current state, but for either button press, you need to advance to some other state that depends on which button it is.

As far as implementation with muxes, it's actually quite straightforward. I would just use four 2:1 muxes to turn the JK FFs into D FFs (drive the K input with the negation of the J input), and then use four 64:1 muxes to implement the state transition table directly — i.e., create a 64×4 ROM out of them — where the select inputs to the muxes are Q3, Q2, Q1, Q0, B and A.

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  • \$\begingroup\$ Indeed, would it work if I had another JK flip flop instead? For example Q would output A and ~Q would output B. \$\endgroup\$ – Xzenon Nov 23 '14 at 16:36
  • \$\begingroup\$ How are the FFs being clocked? \$\endgroup\$ – Dave Tweed Nov 23 '14 at 16:43
  • \$\begingroup\$ I really don't know. \$\endgroup\$ – Xzenon Nov 23 '14 at 16:56
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    \$\begingroup\$ Then perhaps that's a detail you should focus on -- and list as an assumption in your solution. If you OR the two debounced buttons together (using a mux?) and use that as your clock, then yes, the B input is the complement of the A input. If some other clock is running the system, then you have to deal with the three possible input conditions as I described above, and you can't assume that B is always the complement of A. \$\endgroup\$ – Dave Tweed Nov 23 '14 at 17:19
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    \$\begingroup\$ Thanks for the explanation :) Since there's no mention of another clock, I guess I can use the MUX and it would simplify my problem. \$\endgroup\$ – Xzenon Nov 23 '14 at 17:37

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