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I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a number of EDA tools that provide a graphical design browser for your RTL.

What tools area available to draw schematics programmatically either from a verilog or vhdl definition, or from some other text-based input format?

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Use Yosys, the free and open source awesomeness HDL Synthesis Toolbox with extra doses of being cool (and free) (and faster than current-gen Vivado) (did I mention Free as in speech & beer?) (and awesome)!

Get yosys, and the xdot utility (often part of a package called python-xdot) as well as graphviz.

Then, do something like in a verilog file (let's call that minifsm.v):

module piggybank (
                  input         clk,
                  input         reset,
                  input [8:0]   deposit,
                  input [8:0]   withdrawal,
                  output [16:0] balance,
                  output        success
                  );
   reg [16:0]                   _balance;
   assign balance = _balance;
   wire [8:0]                   interest = _balance [16:9];
   reg [5:0]                    time_o_clock;
   localparam STATE_OPEN = 0;
   localparam STATE_CLOSED = 1;
   reg                          openness;
   assign success = (deposit == 0 && withdrawal == 0) || (openness == STATE_OPEN && (withdrawal <= _balance));
   always @(posedge clk)
     if(reset) begin
        _balance <= 0;
        openness <= STATE_CLOSED;
        time_o_clock <= 0;
     end else begin
        if (openness == STATE_CLOSED) begin
           if(time_o_clock == 5'd7) begin
              openness <= STATE_OPEN;
              time_o_clock <= 0;
           end else begin
              time_o_clock <= time_o_clock + 1;
           end
           if (time_o_clock == 0) begin //add interest at closing
              _balance <= _balance + interest;
           end;
        end else begin //We're open!
           if(time_o_clock == 5'd9) begin // open for 9h
              openness <= STATE_CLOSED;
              time_o_clock <= 0;
           end else begin
              _balance <= (success) ? _balance + deposit - withdrawal : _balance;
              time_o_clock <= time_o_clock + 1;
           end
        end // else: !if(openness == STATE_CLOSED)
     end // else: !if(reset)
endmodule // piggybank

and run yosys:

yosys

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2016  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.6+155 (git sha1 a72fb85, clang 3.7.0 -fPIC -Os)

load the verilog file, then check the hierarchy, then extract the processes, optimize, find the state machines, optimize, and show a graph:

yosys> read_verilog minifsm.v
… …
yosys> hierarchy -check;
yosys> proc;
yosys> opt;
yosys> fsm;
yosys> opt;
yosys> show;

and you'll get something like

image repr. logic

With different options to the show command you can also just save the graph to a file. Yosys allows you to write "flattened" logic in verilog, EDIF, BLIF, …, synthesize and map for specific technological platforms, including these supported by ArachnePnR, and do much more interesting things. In essence, Yosys is like letting someone who knows how to build compilers write a verilog synthesizer.

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What do you have? These ones have that feature, with various qualities of output.

  • Synplicity
  • Synopsys Design Compiler
  • Altera Quartus II
  • Xilinx ISE
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  • 1
    \$\begingroup\$ I'm looking to do this on-demand without gui-interaction. I.e. programmatically. I do have access to DC. \$\endgroup\$ – Ross Rogers May 7 '11 at 19:21
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Altera Quartus should be able to do it.

When I was studying VHDL, I've done the reverse conversion sometimes (starting from schematic to obtain the VHDL equivalent) with Quartus Web Edition, and it worked.

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