# Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and incorrect at times

Like,

1. What is the difference between Pin accuracy and Bit accuracy ?

Does pin-accuracy apply to communication interfaces and bit accuracy to computations. Can 't they be used interchangeably ?

2. Is it correct to say that an RTL model has

- Functional accuracy == Pin/Bit-accurate
- Timing accuracy == cycle-accurate ??


Which means that an RTL model when simulated produces precise results at each and every clock cycle. I have come across articles where author says Bit and cycle accurate models simulate faster than RTL models - which suggests that relatively RTL model simulations are slow because they are more precise in terms of functional and timing accuracy.

Can someone explain how(using VHDL or Verilog code) ?