I'm making a long-tailed pair amplifier using a current mirror, the circuit has the following layout: Circuit layout

I simulated it on PSpice and it worked, you can see the bias here: Simulation

I tested it in the real world, on my breadboard, and it didn't work, BJTs saturated (Vc is almost equal to +Vcc), again, you can see the bias here: Real world

So, why this circuit doesn't work in the real world?

Thanks :)

  • 1
    \$\begingroup\$ Double check all your connections and device pinouts. \$\endgroup\$
    – John D
    Nov 25, 2014 at 0:34
  • 1
    \$\begingroup\$ Something is not turned on.. (current source?) I'd much rather use solder than a proto board. (build things in stages if you can.) \$\endgroup\$ Nov 25, 2014 at 0:42
  • \$\begingroup\$ What I don`t understand is the following: You have simulated two identical stages (as far as I can see) with different results: 2.909V vs. 11.8 V. Or is the voltage of 11.8 volts no simulation result? \$\endgroup\$
    – LvW
    Nov 25, 2014 at 10:07
  • \$\begingroup\$ Please add at least the Q1/Q2 emitter voltage to the second diagram, and also Q1 base. I'm guessing Q1 base is open circuit so it drifts towards -12V. You need a DC path from Q1 base to ground (it can be fairly high impedance, allowing 7 uA to flow, but not infinite) \$\endgroup\$
    – user16324
    Nov 25, 2014 at 10:18
  • \$\begingroup\$ Are you sure there are no mismatch problems? have a look at LM3046 \$\endgroup\$
    – 3NZ0
    Nov 25, 2014 at 12:02

1 Answer 1


Zeroeth order:

You said:

I tested it in the real world, on my breadboard, and it didn't work, BJTs saturated (\$V_C\$ is almost equal to \$+V_{CC}\$) . . ."

No. Quite the opposite. BJTs are in cutoff. They want to be in FA (forward active) mode, i.e., the Vbe of both transistors (Q1 & Q2) should approximately equal 0.65V (approx.), just as your simulator shows. Looks like the current mirror is off, because if Q6 was on, it would be pulling current down out of Q1's & Q2's emitters, yielding the proper \$V_{BE}\$ that I previously mentioned. Key question is, what is the voltage across Rrif (5.6K)? I suspect it measures 0V. If all is wired correctly, it should = 14.3V yielding a current of

$$V_{Rrif} = \frac{\left(\left|V_{EE}\right|-V_{BE}\right)}{R_{rif}}$$

    = 11.35V / 5.6Kohm 
    = 2.026mA  (agreeing with your simulator) 

All it would take for you to witness the mal-operation that you do, is for the short-circuit/wire between Q5 collector to Q5 base to be missing/disconnected, or for the wire between Q5 base and Q6 base to be missing/disconnected, or both. Check the wiring all around the current mirror and report back.

First order:

After you get the current mirror connected and working, you will probably next be expecting the 8V+ drop between \$V_{CC}\$ and the collectors of Q1 & Q2, but you may well see a little or a lot of uneveness (maybe as much as Q1 cutoff and Q2 saturated, or vice-versa) depending on the amount of \$V_{BE}\$ mismatch between the xistors. I agree with the poster who said to use the LM3046 which has four (or is it five ? - can't remember) NPN xistors all on one IC; they tend to be closer matched than discrete 2N2222's in separate packages. Even if you do that, you still might not get the seesaw to balance evenly before adding some negative feedback.

One of the problems with analog simulators is that they will apply the same quantities to all the discrete transistor parameters (of the same part number) unless you intervene. So the simulator thinks that all the 2N2222's are perfectly matched. In the real world they are not matched. Sometimes you can see this (this is sorta fun, but be careful) by "squeezing" thumb and forefinger over the case of Q1 or Q2 (not both at once) since \$V_{BE}\$ is very temperature dependent. If the seesaw is uneven but not honked to one extreme or the other, then you will see the seesaw move in one direction or t'other. I say be careful because of the live voltage in the circuit. Also see if you can go into the simulator and change the Vbe of Q1 or Q2 (but not both) and see how little it takes to force the pair out of symmetry at the outputs.

(BTW, what does the subscript "rif" mean in this context?)


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