I just wrote a program to use in PIC16F72. I was trying to simulate it on Proteus and I found that Proteus doesn't have that microcontroller in its library. I read somewhere that PIC16F72 and PIC16C72 are almost the same. So does that mean I can write a program for C72 and use it on F72?

  • \$\begingroup\$ You read somewhere that the two PICs are almost the same? How is reading their datasheets and comparing them not the obvious thing to do!? \$\endgroup\$ – Olin Lathrop Nov 25 '14 at 20:36
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    \$\begingroup\$ Reading the datasheet to you is off topic here. \$\endgroup\$ – Olin Lathrop Nov 25 '14 at 20:37
  • \$\begingroup\$ Just a side note: if you were actually going to use one instead of another, there are some other issues you have to look out for. For example, the current consumption of the F72 is slightly higher. There may be other things. For simulation alone, refer to Majenko's answer. \$\endgroup\$ – user17592 Nov 25 '14 at 22:30

The two chips are almost the same. They use the same instruction set, so yes, you can execute a program written for C72 on F72.

However, there are differences, some of which could be critical:

  • The C72 lacks the ability to read the program memory as data.
  • The C72 is an OTP (One-Time Programmable) chip, not a flash chip.
  • The C72 has an OPTION and TRIS instruction which the F72 doesn't.

The OPTION and TRIS instructions of the C72, while it explicitly states they should not be used to maintain upward compatibility with future devices (which lack them), they may possibly be used by your compiler, which would stop the code working on the F72.

So yes, you may be able to do it, or you may not. Better is to use the official Microchip tools (MPLAB-X, XC8) which gives full support for all their chips.

  • \$\begingroup\$ I hadn't realized that Microchip had made parts which were incapable of setting the TRIS and OPTION registers without using the banking bits. To be sure, in most cases having a means of directly accessing port registers without regard for banking (i.e. having an address where they were mapped identically in all four banks) would be more useful, but given that there's adequate space in the register map, I wonder why Microchip didn't simply allocate space for TRISA, TRISB, TRISC registers in all banks and then have TRIS PORTA be equivalent to `movwf NBTRISA"? \$\endgroup\$ – supercat Nov 25 '14 at 22:25
  • \$\begingroup\$ Probably for efficiency of routing on silicon. You notice that the TRIS and PORT registers occupy the same location in the banks? Makes for simple decoding of the addresses for the IO port hardware. Also, PIC16 is low-end. If you need more efficiency and speed there are faster chips with better facilities, like PIC18, which introduces the LAT concept, and of course the "bigger" chips like PIC24 and PIC32. \$\endgroup\$ – Majenko Nov 25 '14 at 22:30
  • \$\begingroup\$ On the old processors dating back to the PIC16C54, the encoding of "TRIS PORTA" was equivalent to "MOVWF PORTA,W" [except that the assembler only allows "MOVWF" to be specified with the destination bit set]; such an instruction was used because there were no spare addresses anywhere for the TRIS registers to reside. On processors with more I/O space, however, having PORT registers be unbanked would actually reduce the amount of silicon necessary to implement them. \$\endgroup\$ – supercat Nov 25 '14 at 22:41
  • \$\begingroup\$ It's nothing to do with address space, but everything to do with instruction length. The MOVWF instruction can only address 7 bits of address, so banking is needed for that. So you have to decide how best to arrange the registers into that 7 bit range as banks. TRIS and PORT can be differentiated between with just 1 gate (NOT gate) if they are at the same address in adjacent banks. And how often do you need to change TRIS anyway? They wanted to keep some kind of stability between chips, so they needed to provide room in the first bank for commonly accessed peripherals in other chips, while... \$\endgroup\$ – Majenko Nov 25 '14 at 22:48
  • \$\begingroup\$ ...keeping the addresses of all peripherals that exist in multiple chips the same. This meant spreading things between banks. So it's actually a good arrangement that they have that provides ease of address decoding in the silicon, along with stability of addressing between chips. \$\endgroup\$ – Majenko Nov 25 '14 at 22:49

The F72 is the modern version with flash based program memory. The C72 is an older, one time programmable version. As far as simulation goes, they are identical, but for debugging hardware, you would want the F72 to be able to erase and reprogram.


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