I want to design a 4-bit PISO shift register with 4 DFFs and 3 AND gates. I have gone so far that these two designs can be implemented, but I can't go further minimizing it so as to use 3 AND gates for the implementation.
If there is anyone having any suggestions I would appreciate it.
I have thought of another design but I didn't put it here because I think it limits the use of the shift register. Also I think that the second design is not right.
I think that there is another way to be implemented but I am not sure.