Are there any kinds of standards or common practice dimensions which define what BGA escape vias and routing trace/space should look like at 0.8mm pitch? If not, what's the most economical set of dimensions to use?

Several documents I found when searching online discuss vias and routing dimensions on the top and bottom layers, but not inner layers. As I understand it, the inner layers require antipad which makes them more restrictive than the outer layers. Therefore these should be the driving dimensions, but I can't find much on that.

I found a document BGA/PCB Interconnect Design Guidelines that discussed 0.8mm pitch (search for "0.8-mm"). It says that with a hole/antipad of 10/28 mil, only 3.5 mils remain on the planes and that isn't good. It goes on to say that using 8/26 for hole/antipad still leaves only 5.5 mil, and so you should just use microvias.

However, I see some manufacturers offer 8 mil inner clearance (antipad?), so couldn't you use 8 mil holes with a 24 mil antipad and have plenty of ground plane copper left?

I found this NXP document: PCB layout guidelines for NXP MCUs in BGA packages. It has a nice but very confusing table in it. It shows generally standard hole sizes like you'd see from PCB manufacturers (12 mil, 8 mil, in mm) as drill size, and finished sizes way way too small. The pad to drill size for 1mm pitch in particular would be an entirely normal sounding 12/21 via but the 'finished size' is 7 mil! My understanding is that PCB manufacturers operate on finished hole size, not drill size. What's wrong here? (or with my understanding?)

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    \$\begingroup\$ IPC7095B, which can be purchased here for $103, is worth buying. The price is negligible compared to what you will be spending on your board design and PCB manufacture. IPC7095B Table of contents \$\endgroup\$ Commented May 8, 2011 at 11:40
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    \$\begingroup\$ Your PCB shop can work with either finished hole size or drill size. Designs in my shop often specify "hole sizes 10 mil and smaller are drill sizes. Hole sizes greater than 10 mil are finished sizes." Or if we specify a finished size, we give enough tolerance that the hole could be plated completely closed. \$\endgroup\$
    – The Photon
    Commented May 11, 2012 at 16:38

3 Answers 3


I'd love to say there is a simple answer, but there is not, there are too many variables
However you can break the problem down.....

The sizes you select mostly depend on what the capabilities of the fab you are using.
For low cost, reliability, and high yield choose the largest vias and largest traces you can, while keeping annular rings as large as possible and traces well spaced and as wide as possible.

Take a look at the capabilities of you chosen supplier(s) talk to them and ask their advice, after all are the ones that have to guarantee they can make it. e.g. Graphic's Capabilities

Graphic PLC, like others, quote standard, low-yield and development feature sizes.

More than anything else, your escape plan will also depend on the parameters of your PCB.
How many layers do you need? How many rows to you have to escape in your BGA? Generally you need (N/2)-2 layers, where N is the largest number in the number of rows or columns in your BGA. However, if you use microvias things get easier. Remember you don't normally need to escape all the signals, GND and Power can often go direct to the planes.

So, decide: Are using conventional vias, blind vias, buried vias, microvias or microvia-in-pad?
The minium dimensions of the via drill are partly controlled by the layer pair thickness (2:1 is a good starting rule) plus type of PCB material. Harder, thicker materials means bigger drills.
Are you using 18um or 36um copper, you might want the latter if some other part of your circuit carries a high current or perhaps your signal integrity rules play some part in you decision making process? Bigger copper means more undercut which means more tolerance needed.

So first you need to decide what board construction you can stand given your cost constraints in the volumes you are interested in buying, then base your design constraints on that by looking at the capabilities of the fab you want to use and the technology you require.

The reason manufacturers use finished hole sizes is that the drill required is 0.1 to o.2mm larger than the finished hole size. So if you want a 0.5mm finished hole, the manufacturer will drill it 0.7, then plate it down to 0.5 with 0.1mm of copper. So the finished size seems small, but a larger drill can be used.
Don't be so scared of small feature sizes. You will be surprised just how small the drills can be, e.g. Graphic can drill 0.15mm holes using a conventional drill if the material is 0.2mm thick! However, smaller drills are more expensive as they break more often so need replacing regularly (ideally before they break) As they use more of them and being a bit trick, they cost more to replace.

The minimum size of the via pad is defined by the drill size and the drill tolerance. Usually drill size (not finished size) +0.1mm is a minimum. But that depends on yield and manufacturing tolerances. Obviously bigger is better if you have room and you are not working at 10's of GHz.

Ok a worked example:
Using a 358 pin UBGA part, an Altera Arria GX.

Looking at Graphic's data, I can select a 0.25 finished hole (i.e. 0.45 drill) with a 0.45 annular ring. I'll tent the top side.

Excluding power pins, I have 5 rows to escape. Ideally i'll need 4 layers.

Let's try without anything exotic (reducing cost)
vias 0.25 finished 0.45 pad
tracks 0.15mm, min gap 0.1mm
Stock BGA pads on library symbol are 0.45 Not mask defined

That looks like this:
enter image description here

See we managed it on three of the 4 layers, and it looks like we can still make some improvements; We could reduce the track and increase the annular rings or go microvia-in-pad for reduced layer count.

  • \$\begingroup\$ I should have included that the above gives you 0.15mm copper between non-connected pads on the plane layers. \$\endgroup\$
    – Jay M
    Commented May 12, 2012 at 16:04
  • \$\begingroup\$ Excellent answer! \$\endgroup\$ Commented May 13, 2012 at 20:18
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    \$\begingroup\$ @JasonMorgan, Love the answer, I think a bit more formatting work might make it look even snappier in google but you earned the 500, dont spend it all in one place! \$\endgroup\$
    – Kortuk
    Commented May 17, 2012 at 18:41
  • \$\begingroup\$ @kortuk, Electronics and computers are my strong point yet I failed CSE english - that probably shows. Thanks for the points!! \$\endgroup\$
    – Jay M
    Commented May 17, 2012 at 19:36
  • \$\begingroup\$ @JasonMorgan, Over the last 6 or so months this question is our top google hit, it was number 2. I think the improved quality probably has more people linking, thanks for writing this! Hope you decide to keep toying with it when you get bored! \$\endgroup\$
    – Kortuk
    Commented Jun 2, 2012 at 16:37

The simple answer is, it depends which company your buyers use for PWB orders on fine pitch parts.

Added: In my experience, a good buyer & engineer with purchasing leverage in volume can get more significant cost reductions {from qualified suppliers} by negotiation more than by design! However if we are talking new design, baseline costs are usually unknown, but I have seen and made deals like 10% off all std. fab. costs. just by negotiation.

re: 0.8mm pitch BGA device layout recommendations, I offer the following to discuss with your fabricator, if unsure;

Standard BGA design guidelines, IPC 6012B Class 2.

  • Drill Pad Anti-Pad PWB Ratio
  • 6 16 26 39 6.5:1
  • 8 18 28 62 7.75:1
  • 10 20 30 100 10:1
  • 12 22 32 120 10:1
  • 14 24 34 135 10:1 units = 0.001" thick

Please note that most relevant "capabilities": "preferred" and "minimum" trace width / spacing / via hole size / via pad diameter may or may not affect product cost, but "minimum" generally implies lower yields than "preferred" and hidden cost increases in quote will result.

IPC Design Guideline book is essential in your library as ref below. As wel as close communication with your Board shop tech support.

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    \$\begingroup\$ I agree the IPC guide is a bible in the industry, +1 for that. It is an excellent place to start if you are unsure. However personally, I find it always slighty behind the techology used by the fab houses in some areas so talking to them and understanding the reason behind decisions is just as important. If you think about it, it's always going to be the lowest common denominator, but that's not a bad thing. \$\endgroup\$
    – Jay M
    Commented May 17, 2012 at 19:40

Obviously, these dimensions are just what is necessary to escape the BGA pattern. If desired you can change the trace width to hit your desired impedance after you get out from under the BGA. In most cases, the short trace under the BGA will not affect signal integrity significantly.

  • \$\begingroup\$ This doesn't answer any part of the original question. He's asking about vias, not trace impedances. On that note, -1. \$\endgroup\$ Commented Sep 25, 2018 at 15:00
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    \$\begingroup\$ I think you are right but the two things are indirectly related. One via, one trace and two spaces must fit into the 0.8mm pitch. Making the trace narrower allows a bigger via pad but does change the impedance there in a way that should not matter. \$\endgroup\$
    – Pedro_Uno
    Commented Sep 26, 2018 at 20:52

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