Comparison of 180nm and 65nm CMOS technology in consideration of delay, power and energy consumption

Question

how would each of them typically compare with respect to delay, power and energy consumption? (Used in digital circuits)

Answer 1

Above 180 -> 110 nm (depending upon whose process it is) you caould easily follow the scaling rules and get a rough order of magnitude. However, moving to 65 nm and below, several significant changes take place that don't allow direct scaling based estimation to work. Things like high K gate di-electric, Low K-dielectric in the BEOL (Back End Of Line). You really need to compare data-sheets directly, and these are only available under NDA.