I have written a spice code to implement a NAND gate. Then I measured the switch time of that. (The time between change in input which effects the output). I want the rising and falling time to be equal. I tried changing the width of the NMOS and PMOS but I can't find the width in which the rise and fall time be equal. Any idea? Here is my code:

*hello spice 
.include "22nm_HP.pm"

.subckt nand in_a in_b out vdd gnd

.param  Lmin=22e-09
+ wm=44e-09
Mqna w1 in_b 0 0 nmos l=Lmin W= 3 * wm
Mqnb out in_a w1 0 nmos l=Lmin W= 3 * wm
Mqpa out in_a vdd vdd pmos l=Lmin W=wm/2
Mqpb out in_b vdd vdd pmos l=Lmin W=wm/2

X1 in_1 in_X out_11 vdd gnd nand
X2 in_1 in_0 out_10 vdd gnd nand
X3 in_0 in_0 out_00 vdd gnd nand

.param pvdd=2.0v
* Power supplies
Vin_a in_1 gnd pvdd 
Vin_b in_0 gnd 0.0v

vin_X in_X gnd PWL 0ns pvdd 1ns pvdd 2ns 0 5ns 0 6ns 0 7ns 0 8ns pvdd 9ns pvdd 10ns pvdd 11ns 0 12ns 0

vvdd vdd 0 pvdd 
vgnd gnd 0 0

* Control statements
.option post=1
.TR 0.05ns 30ns 

.print DC Vm(out_11 out_10 out_00)

.print TR V(in_X out_11)
.measure tran delay1 trig v(in_X) val='0.5*pvdd' fall=1 targ v(out_11) val='0.5*pvdd' rise=1

.print TR V(in_X out_11)
.measure tran delay2 trig v(in_X) val='0.5*pvdd' rise=1 targ v(out_11) val='0.5*pvdd' fall=1

Vin in gnd PWL 0ns 0 1ns 0 5ns pvdd 6ns pvdd 7ns pvdd 8ns 0 9ns 0 10ns pvdd 11ns pvdd 12ns pvdd 13ns 0 


1 Answer 1


As a general guideline you will want to have the PMOS ~ 2.5X the width of the NMOS (assuming that the lengths are the same). This is because of the mobility differences.

However, I see you are in a smaller process and a node in which some processes implement mobility enhancement in the PMOS, principally through stress. So the guideline may or may not be useful.

Your best bet is to just keep the NMOS at a fixed width and vary the width of the PMOS only. You can also look into the spice file for the process and get the mobility values directly from there.


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