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Can someone please explain the difference between Vio & Vcc and what do they stand for ?

Edit: Modified my question based on the first comment.

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    \$\begingroup\$ Exactly what the datasheet tells you to connect them to. \$\endgroup\$ – Ignacio Vazquez-Abrams Nov 29 '14 at 2:55
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    \$\begingroup\$ Do you have a datasheet that you can link too ? It sounds like Voltage for I/O and Voltage for the IC. But without a datasheet [or a schematic], I can't say. \$\endgroup\$ – efox29 Nov 29 '14 at 3:01
  • \$\begingroup\$ Separating Vio from Vcc is common in FPGAs where the core logic may run at 1.5V or less, but I/O still needs to be 2.5V or 3.3V or a different voltage on each bank, for compatibility with external logic. \$\endgroup\$ – Brian Drummond Nov 29 '14 at 11:19
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Vcc is always the main supply. It is also sometimes called Vdd. The "cc" dates back to when logic chips were made up of transistors; the 'c' is for collector. The "dd" is newer, and refers to the drain pin of a FET.

Vio is simply the power pin for the I/O leads of a chip (when the I/O circuitry is powered separately from the main chip power; this is usually not the case). Separate power supply inputs are often used with transceiver chips that must interface with other circuitry that may have different supply voltages than what is used to power the chip.

An example are the FTDI chips used to interface USB to UART signal levels such as the FT232_BL.

For example, an IC may be powered off of 5v (Vcc), but the I/O lines going to another circuit may run at a different voltage, say 3.3v (Vio). However in other cases, the Vio for the chip voltage may be the same as Vcc, namely 5v. Usually, Vio can not exceed Vcc. logic It is the Vio voltage that determines the thresholds for 1 and 0 for the chip, for example:

high level input: 0.67*Vio to Vio
low level input:  0 to 0.33*Vio

If a chip doesn't have a separate Vio supply (which is usually the case), then these thresholds would be expressed in terms of Vcc.

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