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I'm designing a board for a hobby project where I am using a lattice machxo2 cpld as a system interconnect.

The cpld needs to be clocked at 80-100MHz, and because I sprung for a cheaper cpld, it has no on board PLLs. The easiest way for me to clock it is to use a programmable clock from my main mcu (Atmel SAM4S) to clock the cpld (with a pcb trace of about 3cm).

Because the signal is 100MHz, the slew rate will have to be fairly high, and I'm expecting a lot of ringing. Can I reduce the ringing by adding a small resistor to the output pin of the MCU (10-100 Ohm) and a small cap to ground on the clock line (10-100pF)? According to my back of the envelope math, these values will force the rise/fall time to be around 1ns.

schematic

simulate this circuit – Schematic created using CircuitLab

Will this approach work? Is it common practice? I'm coming from a CS background, so my knowledge is a little shaky.

Thanks.

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I'm assuming this your clock source is a dedicated clock output in on the MCU, so it should be able to handle the slew rates just fine (assuming it is designed for these frequencies). One possible source of ringing might be transmission line effects (or any bad layout issues).

A general rule of thumb is that if your wavelength is greater than 10x the trace length, you can ignore transmission line effects.

A square wave is composed of odd harmonics, so let's take the 5th harmonic at 500MHz. With 2/3 speed of light propagation, the wavelength is ~.4m. This is more than 10x your trace length, so you can likely ignore these. However, considering the 7th harmonic and it's a different story. Now transmission line effects do matter.

The usual technique for getting around transmission line effects is to use matched impedance resistors (not an RC filter). This is relatively easy when you have a cable with a rated characteristic impedance; it's harder for a trace, and is dependent on geometry. For example, I've linked the way to calculate the characteristic impedance of a microstrip. You usually can find calculators online which handle various common geometries.

Since your clock trace will always originate from the MCU, you can place this termination resistor in series with the trace near the clock out pin (again following the rule of thumb of <10x the trace length).

Another way you could gauge how much you need to worry about transmission line effects is with this online transmission line simulator (shameless plug). At the 11th harmonic, the amplitude has decreased to 1/11th the amplitude of the fundamental frequency, so you can use the inverse of the 11th harmonic (909ps) as the rise and fall time. Pick a badly matched R1 (termination resistor) and see if the ringing level exceeds ~10% (or whatever tolerance you deem is acceptable for your application) to determine if you need to worry about termination.

edit:

The reason an RC circuit isn't used is because it doesn't solve the transmission line problem. To illustrate this, I've created two circuits:

Filter near CPLD

The first circuit puts the RC filter at the receiving end of the transmission line (near the CPLD).

enter image description here

I simulated this using various values for C1. R1 and R2 were intentionally chosen to not match the characteristic impedance.

C1 = 100pF (\$f_{-3dB} = 1590 MHz\$)

enter image description here

C1 = 330pF (\$f_{-3dB} = 482 MHz\$)

enter image description here

C1 = 500pF (\$f_{-3dB} = 318 MHz\$)

enter image description here

As you can see none of these are effective at reducing overshoot; they just turn your nice defined square wave into garbage.

Filter near MCU

enter image description here

C1 = 100pF (\$f_{-3dB} = 1590 MHz\$)

enter image description here

C1 = 330pF (\$f_{-3dB} = 482 MHz\$)

enter image description here

C1 = 500pF (\$f_{-3dB} = 318 MHz\$)

enter image description here

It appears like this is an effective technique, however if you look at the 500pF case, the clock edge is becoming more and more like an exponential. Eventually it will decrease the output amplitude, which is not good.

You could build a higher-order filter which is much better at removing just the frequencies above the transmission line limit, but there are problems:

  1. These are really skirting around the real problem, and can't always be used.
  2. These require lots of components and takes up lots of board room. You may even run into transmission line effects before you get to the end of the filter!
  3. A termination resistor is a single resistor, which is not hard to do at all.
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  • \$\begingroup\$ Thanks for linking to your simulation. It was really educational to use. Now, why don't people use the technique of having an RC circuit as a low-pass filter to take out the 5th, 7th, 9th, 11th, etc harmonics? Is the input capacitance of the mosfets sufficient to act as an RC filter? \$\endgroup\$
    – John M
    Nov 29, 2014 at 16:59
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    \$\begingroup\$ @johnny_boy edited answer to include why an RC filter (or any filter) isn't the best solution. \$\endgroup\$ Nov 29, 2014 at 19:26
  • \$\begingroup\$ I wish I could give you another upvote for your amazing answer. I guess I need to read a little more about how transmission lines work because I honestly struggle a little bit with understanding why a single termination resistor helps. (Is it dampening the RLC circuit in the transmission line?) \$\endgroup\$
    – John M
    Nov 29, 2014 at 20:11
  • \$\begingroup\$ Transmission lines are weird things... the traditional method for using a "lumped" model (what we usually do with with circuits) doesn't really work with them. One way to visualize what they behave like it pretend for any time before tdelay the source sees just the characteristic impedance, and after 2*tdelay (time it takes the source to get to the other side and back), they see the load impedance. See: bounce diagrams \$\endgroup\$ Nov 29, 2014 at 21:44
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Both too high or too low slew rate are not good, according to here.

For clock input signals, very slow clock edges pick up large amounts of switching noise from the board and the device. In addition to the noise problem, slower clock edges are more susceptible to jitter, which can reduce already tight timing margins in high-speed designs.

For data input signals, very fast edge rates cause simultaneously switching input (SSI) noise problems on wide data buses. Cross talk problems can also occur.

So, make sure your slew rate not too high, not too low.

Assume your 100MHz clock need a 1.7ns rising/falling time, per the 2 inch/ns rule, your trace should less then 3.5 inch, about 9cm. If you can control your trace length about 3cm, you may not need termination.

However if you must slow down the slew rate (may not because ringing problem but the problems given by the above link), you can use RC circuit. You can refer to this link, p. 2.

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  • \$\begingroup\$ Thanks for providing the links to the above 2 articles. They were both informative and useful. \$\endgroup\$
    – John M
    Nov 29, 2014 at 17:02

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