# IR2110 LTspice simulation weird behaviour

I am obtaining weird voltage behaviour at the gate of my high side mosfet controlled by IR2110 which is controlled by PWM.

PWM configuration:

• Vinitial = 0
• Von = 5v
• Tdelay = 0
• Trise = 7u
• Tfall = 7u
• Ton = 150u
• Tperiod = 200u

For the simulation I use TRTOL = 7 and I am using the "Alternate" solver otherwise timestep is too small.

Here are the schematic and the simulation results: Larger picture: http://i.stack.imgur.com/npxEB.png

Larger picture: http://i.stack.imgur.com/1CNqv.png

The green result corresponds to the mosfet gate voltage and the blue one corresponds to PWM. As you see the gate voltage acts very weirdly.

Is this a simulation problem or would this happen in real life ?

EDIT: I just reduced the load resistance to 10R and gate voltage behaves correctly in 100ms simulation. Seems that is has something to do with the current flowing through the mosfet ... When the current is higher it works better and correctly.

On startup, your bootstrap capacitor C3, C4 need be charged through D2 to VS then R1 to ground. If your R1 is too large, the charging time will be long. Assume R1 = 1k ohms, and C3 = 22uF, then

$$\tau = C3 \times R1 \approx 22ms$$

This causes about 50ms 10% ~ 90% rising time. Because the high side driver supply actually floats on your load, so as the capacitor voltage rising, the lower slope line reflect the voltage change on your load resistance.

When you change the load resistor to 10 ohms, the time reduced to about 500us.

Reduce load 1000R. Is too big to charge de capacitor in enough time.

LO is a output. Leave floating.

Probe gate to source of mosfet too.