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I am new to digital logic and I am confused hot to construct CMOS equivalent for XNOR gate using AND, OR, and NOT gates.

I found XNOR circuit implemented with gates.

And what I did is I plugged CMOS circuits for inverter, AND and OR.

I doubt it is right thing to do.. but I have no idea how to do it other way. Need you help!

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You're correct; that is not the right thing to do. The key is to take advantage of the ability to implement AND and OR via wiring. For example, here's a pull-down network that ORs together the results of two AND operations:

schematic

simulate this circuit – Schematic created using CircuitLab

Note that the OR doesn't require any extra transistors at all. ANDing together two ORs is similar. Using this method, you can implement ~(A~B + ~AB) using twelve transistors, including the inverters. There are more efficient ways that use transmission gates or dynamic logic, but I don't think you can go below twelve in traditional CMOS logic.

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  • \$\begingroup\$ I'm pretty sure that circuit doesn't work properly. Won't it leave the output floating when it's supposed to be high? \$\endgroup\$
    – user39382
    Commented Nov 30, 2014 at 4:39
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    \$\begingroup\$ Yeah, that's why I said it's just the pull-down network. The pull-up network is complementary and can easily be derived from the PDN. I was trying to avoid giving too much information for what might be a homework problem. \$\endgroup\$
    – Adam Haun
    Commented Nov 30, 2014 at 4:50
  • \$\begingroup\$ I cannot understand it. I never did digital logic before.. :( Can you give more details? This is type of problem I cannot even find right datasource to look for...totally confused \$\endgroup\$
    – YohanRoth
    Commented Nov 30, 2014 at 5:02
  • \$\begingroup\$ What's your motivation for asking the question? Do you understand the basics of how CMOS inverters and NAND/NOR gates work? \$\endgroup\$
    – Adam Haun
    Commented Nov 30, 2014 at 23:37
  • \$\begingroup\$ If one doesn't mind loading the inputs, an NMOS xnor gate only requires two transistors and one passive pullup. Even adding inverters to buffer both inputs only increases the tally to four transistors and three pullups. I don't know if any practical NMOS devices used such a design; it's interesting that it really doesn't translate to CMOS very well. \$\endgroup\$
    – supercat
    Commented Apr 30, 2015 at 18:20

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