# VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components.
When I simulate my VHDL design (a combinational circuit) using ModelSIM, there are no delays displayed in simulated WaveForms.
I want to know how can I add delay to elements of UNISIM library and then see its effect on MODELSIM simulation?

• There are three types of simulation: (a) behavioral simulation, (b) post map simulation and (c) post place&route simulation. Depending on the type, the tools use different libraries and delay models. Which type do you use? – Paebbels Nov 30 '14 at 18:34
• I guess I have run behavioral simulation, however how can I run post map simulation in ModelSIM for Xilinx/UNISIM components? – VSB Dec 1 '14 at 6:11

Each synthesis step generates it's own simulation model. So start start place&route and select 'generate post par simulation model' afterwards. Now you can launch your selected simulator iSim or vSim from ISE.

You need to attach the generated SDF file when invoking the simulator (On ModelSim : Start Simulation ... / SDF panel")

http://en.wikipedia.org/wiki/Standard_Delay_Format

This file looks like EDIF netlists or LISP code (full of parentheses), its purpose is to tag each primitive with delay parameters.

The right way to do simulation considering components delay in ISE is to:

1. Compile simprim and XilinxCoreLib using compxlib command
2. Do post-route simulation e.g. (anything other than behavioral simulation have built-in delays involved)