3
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Following code I tried on EDA playground with command appended with +define+DEBUG but DEBUG switch doesn't seem to be working. Its always block is sensitive to error and this variable is changing four times here but still the block is not being sensitive.

http://www.edaplayground.com/x/7Cg

module test;      
  integer error;
  event err;

  initial
  begin
      #10 ->err;
      #10 ->err;
      #3 ->err;
      #1 ->err;
      #10 finish(error);
      $display("%d",error);
  end

  initial error=0;

  always@(err)
  begin
      error=error+1;
  end

  always@(error)
  begin
    `ifdef DEBUG
      $display("Error at %d",$time);
    `endif
  end

  task finish(wrong);
    integer wrong;
  begin
    #10 if(wrong==0) $display("-----------TEST PASSED-----------");
        else $display("---------------TEST FAILED---------------");
  end
  endtask  
endmodule
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1 Answer 1

2
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+define+DEBUG is a compile time argument, not a run time. Moving +define+DEBUG to the appropriate line will fix the issue. See http://www.edaplayground.com/x/7ES

FYI: SystemVerilog has $test$plusargs/$value$plusargs which will allow run time arguments. Example with run time argument +DEBUG: http://www.edaplayground.com/x/5zF

always@(err) begin
  error=error+1;
  if($test$plusargs("DEBUG")) begin
    $display("Error at %d",$time);
  end
end
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1
  • \$\begingroup\$ I am interested to know some examples wherein how the compiler directives and defining text macros can be useful in verilog. \$\endgroup\$
    – Abhi
    Commented Dec 2, 2014 at 7:33

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