0
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Code

module block;
  reg a;
  reg b = 1'b0;
  reg c = 1'b1;

  initial begin
    c  = b;
    a <= c;
  end

endmodule

output

I simulated the code fragment shown in figure expecting the value of a to be 1'b1 because the statement a <= c; is nonblocking and the RHS of the statement is evaluated at the beginning of time step(i.e before execution of c = b;).

But this is the result I obtained. Why is the output a 1'b0 and not 1'b1?

PS: I know it's not a good practice to mix blocking and nonblocking statements in the same block, but I wanted to know how the IEEE std explains this special case.

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1 Answer 1

4
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You have given c a default value of 1, but then at time 0 assign it to be equal to b (blocking). So the simulation copies the value of b to c before sequentially moving on to perform a <= b.

What you have written is essentially:

module block;
  reg a;
  reg b = 1'b0;
  reg c;

  initial begin
    c  = b;
    a <= b;
  end

endmodule
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5
  • \$\begingroup\$ So is it like the initial statement reg c = 1'b0; doesn't have any effect in the code because the blocking statement also covers it's assignment simultaneously? \$\endgroup\$ Commented Dec 3, 2014 at 12:59
  • 1
    \$\begingroup\$ @srvn11 yes. initial values assigned like that are often not considered to be synthesizable. Although they probably work for setting FPGA defaults. setting defaults in an initial block for FPGA use is quite common. both types are meaning less for ASIC use, then you should use an active low async reset. \$\endgroup\$ Commented Dec 3, 2014 at 14:36
  • \$\begingroup\$ thank you for the info... I just have one more doubt! The RHS of a nonblocking statement is evaluated at beginning of time step and assigned to LHS at end of time step right? So here value of a should be default value of c i.e 1'bx right? But here it's taking value of b. \$\endgroup\$ Commented Dec 4, 2014 at 4:23
  • \$\begingroup\$ @srvn11 Your description of non-blocking (<=) is correct. But code is executed sequentially, Blocking(=) is placed first so is executed first. And that is why it is bad to mix styles in the same block because if you flip-the order of the statements you get a different behaviour even though you think you describing parallel hardware! \$\endgroup\$ Commented Dec 4, 2014 at 9:09
  • \$\begingroup\$ Just seeing this great question and wanted to confirm. Is what's happening that the right-hand side of the a <= b nonblocking statement being evaluated in the "Active region" (this is the language Stuart Sutherland uses) and so we get c == b = 1'b0 by the time we arrive at that second a <= b nonblocking statement to evaluate the RHS? Then the assignment to a happens in the subsequent "Nonblocking Assignment update region"? Thanks again for your very helpful answer here! \$\endgroup\$
    – EE18
    Commented Feb 3 at 13:50

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