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I'm designing a chain of Xilinx FPGAs. There are many (e.g 32 or more) devices with short distance (about 10~15 cm) that I want to connect them together in a chain. I'm not sure about TMS and TCK signals integrity. Each device has buffers in JTAG I/Os, should I use other buffers for TMS and TCK in the middle of path because of long distance between near and far devices?

TDI, TDO removed for clarity

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You should read through the relevant Xilinx documentation; for Spartan-6's that would be UG393 (Spartan-6 FPGA PCB design & pin planning guide), UG380 (Spartan-6 Configuration), and possibly others. No doubt Xilinx have similar documentation for their other product lines.

With regard to your particular problem, there is some fairly specific advice in those documents on how to lay out the JTAG clock. I also strongly recommend that you use a series termination resistor (22-100 ohms) on each TDO->TDI link, as close as possible to the TDI pin.

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I think it's not a good solution to build a chain of 32 FPGAs. You should also consider the time for programming/reprogramming 32 FPGAs. I don't know the coast, but maybe you can add several USB to JTAG converts and a USB-Hub to your board. Other vendors employ a complete auxiliary FPGA for this job.

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Xilinx development boards are equipped with FTDI usb-gpio chips which can speak gpio, rs232 and lpt. These chips are reconfigure at usb hot-plug detection time with an alternative firmware to speak JTAG.

Alternativly, you can use a JTAG programmer PCB from digilent (JTAG-SMT1). This surface mounted PCB comes with drivers and tools for Digilent Adept and Xilinx tools like impact or chipscope.

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  • \$\begingroup\$ Thanks, do you have any example of that converters? \$\endgroup\$ – Hadi Dec 3 '14 at 18:04

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