# Scaling 12V PWM signal to 0-10V

I'm trying to translate a 3.3v PWM signal through an optocoupler to the 12V side of a circuit, filter it to obtain a relatively clear DC voltage, and scale that to 0-10V for a control element.

So far, my circuit looks like this: The square wave gen is emulating the PWM signal, the resistive divider should scale the voltage from 12V to 10V and the RC filter should re-create the variable DC voltage from the PWM signal.

What I'm experiencing though, is that at 50% duty cycle, the filtered output is not 5 volts as expected, but slightly lower, at 4.69V.

What is the source of this inaccuracy? What do i need to take into consideration to make a reliable linear output?

• Could be lots of things. Have you measured the 12V supply and the 10V at the resistor divider? Have you measured the duty cycle? Slow or asymmetrical rise and fall times can impact your filtered signal as well. Dec 5 '14 at 19:31
• The capacitors in the Falstad circuit simulator default to an inaccurate model. You can click and choose the accurate one. Dec 5 '14 at 19:58
• Your charge/discharge paths to the C in your RC are not symmetrical. Charge path is through 4k7 + 2k1 in series, whereas discharge is through 4k7 and your transistor. You'd be better off using a 5-12v level shifting circuit to drive into the RC and limit your PWM to 83.3% Dec 5 '14 at 20:00

When it is charging (input to the transistor low), it is charging towards 10V through a resistance of 6.45K ohms (the Thevenin equivalent source resistance of the divider plus the 4.7K resistor), and when it is discharging (input to the transistor high) it is discharging through a resistance of 4.7K ohms (to maybe 50mV- the VCE of the saturated transistor- it won't make much difference so I'll guess at it- you can refer to the datasheet for a slightly better value).

For steady state, assume the voltage is fixed (does not change during a cycle), so we know the current charging must equal the current discharging if the times are equal (ask if that is not obvious).

So (10 - Vc)/6.45 = (Vc - 0.05)/4.7

solving, Vc = 4.244V. (Even worse!) I don't know where the value in your simulation comes from but there will be lot of ripple in the voltage with such a small capacitor. Figure about 0.001 second * 0.9mA/10^-6 = 0.9V, so +/-450mV ripple (about 10%), so perhaps it's the peak voltage, not the mean-> 4.244 + 0.45 = 4.694, which agrees with your simulation.

You can use a more symmetrical drive either by increasing the 4.7K to a much higher value or using a CMOS buffer that will also get rid of the Vce(sat) term. Just remember that the buffer does not make this issue magically go away, and if you have a relatively low resistance compared to the buffer output impedance, and that impedance is asymmetrical (as it usually is) you may not see the exact voltage you're expecting.

Note that using a highly asymmetric switch like this one introduces a significant nonlinearity, which may be undesirable. In this case, it's about -15% of signal at mid-scale or -7.6% of full scale.

• It makes very little difference to the computation, but 50mV seems low for saturated $V_{CE}$. Dec 6 '14 at 3:57
• @copper.hat Check out the datasheet for a 2N4401 and see what it tells you for Ic = 6-7mA and Ib = 2.5mA. Try figure 4. Forced beta is less than 10 in this circuit. It's a pretty good guess. Dec 6 '14 at 4:13
• Thanks Spehro, I was sloppy. (Amusingly, I had looked at exactly the same datasheet when I wrote the above). I had just looked at the max value which was around 0.4V @150mA. Dec 6 '14 at 4:20