Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows

|OPT code|rs|rd|immediate|

|6 bits |5 bits|5 bits|16 bits|

The OPT code is the instruction type(lw), rd is where the value will be loaded to, rs is the base register and immediate is the offset. Mips support only displacement mode meaning:

 lw $t9, ($t7)60

is the same as


This is a typical mips load but what if i wanted to implement address indirect load in the control unit, writing the misconstructions for address indirect mode similar to a basic cisc computer. Where the the address of the value is in memory. is this possible to do in one instruction?


This is what i am looking for in one instruction:


or better yet

  • \$\begingroup\$ I'm not sure I entirely follow you. Can you write a pseudo-instruction to demonstrate what you mean? Is it Reg[$t9]<-M[addr] that you are after? \$\endgroup\$
    – Majenko
    Dec 8, 2014 at 9:43
  • \$\begingroup\$ yes this is exactly what i am after \$\endgroup\$ Dec 8, 2014 at 10:12

1 Answer 1


Not as one single instruction, no. Basically because MIPS, as a 32-bit instruction, doesn't have room to hold both an op-code, a target register, and a 32-bit address.

Even though your specific system may have just 26 physical address lines, internally it's still a 32-bit addressing scheme. Those 26 address lines may represent the lowest 26 bits of a 32-bit address, or they may be mapped into different areas of the 4GiB address space through an MMU of some form.

To load a value from an address into a register you first have to load the location into a register, then load the value from memory relative to that register.

If the value you want happens to lie within the first 32768 bytes of the address space, then you can access it relative to the zero register (an offset is signed, so you only 15 bits of it are valid for the lowest portion of memory). A negative offset from zero would yield you access to the upper 32767 bytes of (32-bit) memory space.

The whole point of RISC as opposed to CISC is that you have a few very basic instructions that you chain together to do what you want, rather than a single instruction that does the whole thing for you. In RISC there are very very few instructions that take more than one clock cycle to run (only really the branch instructions are longer), whereas in CISC instructions may take many more cycles to execute. In RISC you use just the clock cycles you need for that one specific task, and you don't waste clock cycles on extended length instructions that do what you want plus other things that might be useful in other situations.

Also, RISC makes for better multitasking since each instruction is generally just one cycle, so interrupts can happen faster. With CISC, if an instruction takes, say, 20 cycles to execute, the system can't execute an interrupt until it's finished that instruction.

  • \$\begingroup\$ For the classic 5-stage pipeline, loads take two cycles (the MIPS R2000 actually had a load delay slot). A processor can begin an interrupt before a previous instruction has completed; this is easier if it can be determined early if the instruction generates (or is likely to generate) an exception (e.g., MIPS R4000 had FP conservative exception detection before the integer pipeline's writeback stage, simplifying precise exceptions). However, it is also possible to speculate that an exception will not occur. Even RISCs can choose not to stall on a load miss. (+1 for almost completely right) \$\endgroup\$
    – user15426
    Dec 8, 2014 at 23:26

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