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Suppose I have a small (4cmm x 4cmm) 4-layer PCB with standard stack-up of Signal-Vcc-Gnd-Signal. The board is dominated by two QFP-100 (FPGA and uC) on both on top and bottom side of the board with various traces running underneath each of the chips.

Both FPGA and uC are powered from the same 3.3V rail. Now I'm whether I should

  • simply connect each power pin and associated capacitor to the Vcc plane by vias OR
  • form a Vcc island on top and bottom side under the ICs and connect this island to the Vcc plane at one point, possibly via a chip bead. The decoupling caps would then connect to the Vcc island and have the other leg connected to the Gnd layer by vias. OR
  • form a Gnd island on top and bottom side under the ICs and connect it on a single place to the Gnd plane. Each Gnd pin would then connect to the Gnd island and each Power pin would be tied to the Vcc layer by vias. Same for the decoupling caps.

In either of the two last cases the island would inevitably contain some cuts and holes.

There is no exceptionally sensitive analogue circuitry on the board except for the ADC inside the uC. Still I would like to have the supply/ground as quite as reasonably possible.

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Since you are planning to have the two ICs back to back in the circuit board you cannot use the typical technique of putting the bypass caps under the ICs. Also since the two ICs are gull wing leaded parts the best approach is to place the bypass capacitors for each chip right next to the PWR/GND pins of the IC so that there is direct copper connection from the cap to the IC pads. Then connect each PWR and GND pin with vias down into the internal VCC and GND layers.

Since the space under the QFP-100s will largely not be useful for routing out signals you can arrange to place most of your PWR and GND vias under the ICs instead of outside the IC pin perimeter. If there are some connections between the MCU and the FPGA you could use some of the space under the ICs to interconnect MCU to FPGA. I would suggest that you complete these connections in the layout before committing to the final FPGA pinning so as to optimize the routing under each IC. In any case strongly resist the temptation to cut up the PWR and GND layers to add interconnection signals in those layers, especially under the two ICs.

Since your MCU has a ADC it probably also has a pair of separate VCCA and GNDA pins. Carefully plan any analog circuitry so that the bypass and any island that you create for these is outside the periphery of the MCU. Aim for having the bypass caps for these be the same as the others (copper direct from caps to IC pins). You can then place single point GND connections for this analog copper at the IC pin - possibly under the IC just inside the IC pad - into the common GND plane.

As you plan a small layout like this it can be good to also allow flexibility on the size selection of bypass capacitor packages. In some cases it may be useful to select 0402 or 0201 packages because of directly adjacent PWR / GND pins. In other cases where there may be signal pins in between the power pins select a larger SMT capacitor so as to bridge the space between the PWR / GND pins and allow routing of signal traces into the IC chip in between the capacitor pads.

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  • \$\begingroup\$ How bad are cuts in the Vdd plane? Some of those will probably inevitable... \$\endgroup\$ – Arne Dec 9 '14 at 16:15
  • \$\begingroup\$ The less the better. And if you have to make long ones make sure to break the trace up into sections so that the power plane is not fully cut open. Make the tradeoff of a few extra vias in the trace in exchange for keeping your VCC plane as gridded as possible. \$\endgroup\$ – Michael Karas Dec 10 '14 at 2:56
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I would go with option 1 vias for everyone, separate vias no sharing. Your goal is to minimize the impedance between your power and gnd layers, and your pins and your caps. In the second two options, assuming you don't carve up those islands you would still have a low impedance connection between your pins and caps. However you have half the vias of solution one, so your total via impedance will double.

Remember you want to keep your caps and your pins as "electrically" close as possible. The lower the impedance between power and ground the less ripple voltage you will see.

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  • \$\begingroup\$ With Vcc islands connected to the Vcc by a ferrite bead I hope to reduce back-emf. \$\endgroup\$ – Arne Dec 9 '14 at 15:05
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    \$\begingroup\$ @Arne - Reserve the use of the ferrite beads for island isolation to just the Analog area of your design. For the digital sections you do not want ferrite beads between the ICs and the PWR / GND plane. Instead use the ferrite beads between the plane connections and the PWR pins entering the board. Leave the GND entry pins to the board hard copper without series ferrites. \$\endgroup\$ – Michael Karas Dec 9 '14 at 15:13

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