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Before I get to my question, I'll just go over the input and output of the circuit from what I "know". The base of the BJT gets a 20 microsecond pulse that puts the bjt well into saturation and "VOUT" goes into a unity gain buffer to be measured somehow.

Questions: At steady state, both C1 and C2 should have 9V from plate to plate on each of them, correct? Then, while the base of the BJT gets a pulse and is in saturation with VCE(sat) = 0.5v, the voltage on the opposite plate of C1 goes from 0 to -7.5? What does this cause to happen at C2 and how do I calculate the voltage drop across the resistor between them?

I hope that's enough information to give you an understanding of my lack of understanding. Thanks.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ You do know that the tool you used to draw the schematic is also a simulator, right? And why wouldn't the two capacitors have the full 9V across them in the steady state? \$\endgroup\$ – Dave Tweed Dec 9 '14 at 20:18
  • \$\begingroup\$ I prefer to understand why things happened rather than just simulate it and take it for magic. That's why I asked how to calculate it, so I can understand the result of the simulation or design to begin with. Yes, I'm very familiar with CircuitLab, I used it while it was in free beta on their own website. You're right about the typo of 8V it should have been 9V. \$\endgroup\$ – Jon Clark Dec 9 '14 at 23:23
  • \$\begingroup\$ The point is, running the simulation and seeing the voltage and/or current waveforms at each node can give you a lot of insight into the underlying processes. The simulator isn't doing anything you couldn't do by hand, but it runs faster and makes fewer mistakes. See if you can explain everything your see in the simulation results. If not, come back here and ask specific questions. \$\endgroup\$ – Dave Tweed Dec 10 '14 at 13:07
  • \$\begingroup\$ Sorry, I realize my question is fairly open ended based on my initial explanation. I'm concerned with the period of time after the BJT saturates and the voltage on the inner plate of C1 changes to -9V+Vce(sat) and things appear to settle. The simulation shows the inner plate of C2 at a potential of about -5V. I'm assuming the change in potential of C1 causes current to flow from C2 to C1 accounting for the voltage drop across the resistor but I'm not sure how to calculate it. Would the simplified model at that point just be a cap discharging into a cap through a resistor in series? \$\endgroup\$ – Jon Clark Dec 10 '14 at 19:01
  • \$\begingroup\$ I don't know why you're seeing only -5V. See my analysis below. \$\endgroup\$ – Dave Tweed Dec 10 '14 at 19:55
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In the instant after the transistor turns on, you can treat the two capacitors as voltage sources. So, in order to calculate the voltages across the circuit in the instant before the voltages start to change on the capacitors, you can simply start adding up voltages: +0.5 V at the collector of Q1 and -8.5V on the left side of R4. Note that the current through R7 is of no consequence initially; it affects the time constant of the voltage decay across C1, but not the initial conditions.

Now, R4 and R6 form a voltage divider, so you can simplify that part of the circuit by replacing them with their Thévenin equivalent: -7.73V and 909Ω. Now you can calculate the current flowing through that impedance in series with R2, which is 7.73V/(909Ω + 4000Ω) = 1.575 mA. Note that the voltage across C2 exactly cancels V1 at this moment in time.

This gives you the voltage drop across Rth and R2, which is 1.43V and 6.30V, respectively. This should give you -6.30V at the right side of R4 (NODE1), and +2.70V at VOUT.

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  • \$\begingroup\$ Thank you very much! It'd been so long since I'd looked at a problem like this. I definitely hadn't thought about using thevenin equivalent circuits in a long time. \$\endgroup\$ – Jon Clark Dec 11 '14 at 17:20

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