Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I've been looking around for some kind of explanation on how to get the output DC voltage on a single ended differential amplifier with active load like the one in the image 
It's just that i don't really understand how the DC voltage is fixed there. It seems it's kinda randomly set, because neither M4 or M2 have their VDS fixed.
I would appreciate any help you could provide. Thank you!
Because it's a differential amplifier.
M5 provide the bias current \$I_{Q}\$ for the differential pair formed by M1 and M2. When a common-mode voltage of \$v_{cm}\$ applied to M1 and M2's gate, the current \$I_{Q}\$ splits evenly between M1 and M2. Just this current biases the transistors.
Without any load at the Vout node we cannot explain the real function of the circuit. At the top of the diagram (M3, M4) we have a conventional current mirror that forces both currents to be equal. On the other hand, the currents through M1 and M2 are equal only for a common mode voltage at both inputs. If there is a voltage difference, both drain currents are NOT equal (but the current mirror "wants" to keep them equal).
What is the result: The current difference goes through the load connected at the Vout node (which may be another amplifier stage).
If there is no load resistance connected at the Vout node the internal FET resistances ro (inverse slope of the output characteristics) come into play forming a kind of ohmic load resistance (and, thus, fixing the DC value).
EDIT: Supplementing the above explanations, we have to realize that the current through the current mirror (in particular, through M3) belongs to a certain fixed gate-source voltage VGS (for M3: identical to the drain-source voltage VDS). This clearly determines/fixes the DC voltages in the rest of the circuit.
