Without any load at the Vout node we cannot explain the real function of the circuit.
At the top of the diagram (M3, M4) we have a conventional current mirror that forces both currents to be equal. On the other hand, the currents through M1 and M2 are equal only for a common mode voltage at both inputs. If there is a voltage difference, both drain currents are NOT equal (but the current mirror "wants" to keep them equal).
What is the result: The current difference goes through the load connected at the Vout node (which may be another amplifier stage).
If there is no load resistance connected at the Vout node the internal FET resistances ro (inverse slope of the output characteristics) come into play forming a kind of ohmic load resistance (and, thus, fixing the DC value).
EDIT: Supplementing the above explanations, we have to realize that the current through the current mirror (in particular, through M3) belongs to a certain fixed gate-source voltage VGS (for M3: identical to the drain-source voltage VDS). This clearly determines/fixes the DC voltages in the rest of the circuit.