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Most sources on the internet discuss routing signals over a split power plane and how to do this properly. The main solution here is to create a short return current path. I'm wondering whether routing signals over a split power supply plane (not ground plane) will have any noticeable effect on the signal integrity and if i should take measures.

My situation:

4-layer PCB:

  • Top layer: signal
  • Internal plane: splitted ground (analog/digital)
  • Internal Plane: splitted power supply plane (3.3V digital and 3.3V analog are relevant in this case)
  • Bottom layer: signal

I'm routing a few clock signals at the bottom layer starting from the digital section to the analog section. The signals will cross the power plane split between the digital and analog section (gap is 0.5mm wide). I will provide a solid current return path on the ground plane (bridge between digital and analog) so return currents shouldn't be an issue.

The clock signal is just above 12MHz, the traces are 0.2mm wide and a maximum length of 13.4cm. The traces are terminated with a series resistor.

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The quick answer:

Any signal that crosses a split in the power OR ground plane is bad. The higher the switching rate (and the faster the signal edges are), the worse the effects will be.

The long answer:

When you say, "I will provide a solid current return path on the ground plane (bridge between digital and analog) so return currents shouldn't be an issue", either you don't understand the issues, or I didn't understand your statement. The reason that I say this is that you can't have a "solid current return path" and still have a split plane. There has to be some non-solid-ness in there.

The return currents will flow on the closest power OR ground plane to the signal. So in your case, if your signal is on the the top layer then the return currents will be on your ground layer. But if your signal is on the bottom layer then the return currents will be on the power layer. For most medium to high speed signals, the return current will follow the signal trace, and not take the shortest path. To put it another way, the return currents will try to minimize the "loop area".

If your signal switches from the bottom to top (or vise versa) then the return currents will also switch, flowing through a decoupling cap. This is why it is important to sprinkle decoupling caps all over the PCB, even when it's too far away from a chip to make any difference on power.

Minimizing the loop area is critical for signal integrity, minimizing EMI, and reducing the effects of ESD.

If your signal cuts across a split in the power/ground plane then the return currents are forced to take a detour. In some cases, this detour can increase the loop area by 2x or even 10x! The most simple and best way to avoid this is to not run a signal across a split.

Some boards have mixed analog and digital planes, or on some systems have multiple power rails. Here's a list of things that might help out in these circumstances:

  1. For things like clocks or active data lines, you really don't want to cross a split. Some creative PCB routing is the best solution, although sometimes you just have to have a combined analog/digital plane instead of splitting it.

  2. For low-speed signals, or signals that are mostly DC, you can cross a split but be careful and selective about it. If you can, slow down the edge rate using a resistor and maybe a cap. Usually the resistor would be physically bridging the split.

  3. Things like 0-ohm resistors, or caps, can be used to provide for a signal return path between two planes. For example, if a signal does jump the split, adding a cap between the two planes near the signal can help. But beware, if this is not done well then it could negate any positive effects of having a split in the first place (I.E., keeping the digital noise from going to the analog plane). The nice thing about using caps or 0-ohm resistors for this is that it allows you to play around with the design after the PCB has been made. You can always stuff or unstuff parts to see what happens.

While many PCB designs will involve some sort of compromise, try not to compromise unless you absolutely have to. You'll have less headaches, and loose less hair, by doing that.

I should also point out that I completely glossed over the issue of impedance changes due to the split, and what that would mean. While important, it's not as important as minimizing the loop area and stuff. And understanding the loop area is much easier than understanding how the impedance changes will effect the signal integrity.

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  • \$\begingroup\$ If you absolutely must use a cap to "stitch" split planes together, make sure you attach the cap to either side of the plane. Engineers have a bad habit of assuming one leg of a cap is always attached to GND and the other to some VCC, when in reality you'd be connecting both sides to GND or both sides to VCC, depending on the plane you're stitching. \$\endgroup\$ – ajs410 May 13 '11 at 17:26
  • \$\begingroup\$ I was assuming that the return current would go through the nearest/shorted ground path and not nessecary the power plane which seems to be wrong \$\endgroup\$ – Bianco Zandbergen May 13 '11 at 17:31
  • \$\begingroup\$ @Bianco, it will follow whatever path minimizes inductance. What we call power is still a plate of meta held at a constant voltage and will form the return path. That is because at your chip there should be decoupling caps, the signal can use these to "complete" the circuit if needed. Often you are switching a power signal also, in which case the caps will not be needed. \$\endgroup\$ – Kortuk May 14 '11 at 1:18
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I've got to kick some conventional wisdom to the curb. At least for the RF boards I've done, I've found that performance is improved by not having split grounds for analog and digital. Instead, using a solid ground plane and doing ground pours to keep a low inductance/low resistance path to a single unified ground node has worked better for the types of products I've done, primarly small size (handheld) and RF heavy (receivers and transmitters in the 500 MHz range and up.

I typically don't use Power planes, as it doesn't take much trace width to drop any trace IR voltage drop to the microvolt range, and I'd rather have ground there.

Just another approach.

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  • \$\begingroup\$ I read advice like this regularly and I am of the opinion that those whom do not get better results with a split plan are not doing it right. Designing a high speed RF board is serious business, designing a high speed RF board with separate analog and digital grounds is more serious business. This is an opinion, but with great design practice and a tedious design a separated board can receive benefits for your analog system. Those digital lines just generate so many frequencies. If you have very low speed digital then you digital does not need to segregate. \$\endgroup\$ – Kortuk May 14 '11 at 7:16
  • \$\begingroup\$ I think it, like most of engineering is not an easy task that has the same solution space every time. That is why they pay engineers well. \$\endgroup\$ – Kortuk May 14 '11 at 7:17
  • \$\begingroup\$ @Kortuk-The double negative is a bit confusing. I take it you are saying that if you do it right, a split plane will give you better results? That's not my experience, but you are correct that there isn't the same solution space every time, which is maybe the bigger point! You have to start with a good floorplan, separating analog, digital and power supplies as much as possible to start with, or you're swimming upstream... \$\endgroup\$ – rfdave May 14 '11 at 12:54
  • \$\begingroup\$ @Kortuk: Howard Johnson in "High Speed Digital Design" advocates for a single ground plane pretty strongly. \$\endgroup\$ – darron May 16 '11 at 23:27
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One might ask - why is a clock signal going into the analog region? Perhaps you need to gerrymander your planes to bring digital ground to the digital sides of your DAC/ADC's (I'm assuming that' what's going on here.)

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  • \$\begingroup\$ It are indeed the clock signals for ADC's. The crystal oscillator inputs resides at the analog part of the chip. I have chosen not to use an external crystal but providing an external clock signal. This signal is centrally generated in the digital section and distributed all over the board via a buffer. \$\endgroup\$ – Bianco Zandbergen May 13 '11 at 17:25
  • \$\begingroup\$ @Bianco, that sounds like the source of a large amount of noise issues. High frequency clocks are the devil in the details. \$\endgroup\$ – Kortuk May 14 '11 at 7:12
  • \$\begingroup\$ I'm reworking my design now to use multiple clock sources instead of a central one. I want to avoid unnessecary taunting with the devil. \$\endgroup\$ – Bianco Zandbergen May 14 '11 at 18:47
  • \$\begingroup\$ Besides the clock signal, your ADC data lines will also have to be connected -- many ADC's are designed to have separate DGND and AGND, and to separate the digital pins from the analog -- you can then split the ground planes right under the IC's (see analog.com/static/imported-files/tutorials/MT-031.pdf figure 8) Does that separation not exist in your ADC's? \$\endgroup\$ – Toybuilder May 16 '11 at 4:38
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Clocks should not go through vias. There's an inductance and capacitance price that you pay when you use vias and as your clock frequency increases this will eventually bite you. It also forces the clock's return currents through a decoupling cap. It really is just best practice to keep the clock all on one layer.

This is in addition to the advice above.

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  • 1
    \$\begingroup\$ It really depends on the board. For a 4 layer PCB, you're absolutely correct. For boards with more than 4 layers, it might be better to put your clocks on an inner layer (between the power/ground planes). If there is a signal layer between the top and the first plane then the impedance of traces on the top will be terrible so putting the clock on a different layer could be a plus. And finally, for BGA's you often can't fan the signal out without going to an inner layer-- in which case you don't have a choice. It helps to put a cap near the clock via, to reduce the loop currents. \$\endgroup\$ – user3624 May 13 '11 at 17:48
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Depending upon the speed of the clock and its routing, I would expect that you might benefit from passing it through a device at the boundary of the two planes, the input of which is relative to the digital plane and the output of which is relative to the analog plane. If the clock is used for many purposes, you could also gate it there so that only the clock pulses that were actually relevant to the ADC would pass through the boundary.

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Routing your clock over split power planes will have a negative impact. As some others have mentioned it's better to use one solid ground plane and partition your analog and digital routing to keep them isolated. I would be concerned about EMI with your clock going over a split plane (looks like a slot antenna) and you may want to consider changing from series termination to parallel for your clock line.

I'm not saying that crossing split planes in this type of setup can't be done but you should take care and understand that there will be risk involved that you're not going to be able to easily quantify.

If you are going to keep your layout the way it is I would like at some app notes by the ADC guys like Analog Devices (or your ADC vendor chip) to see what recommendations they have for doing this type of split plane layout.

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Sadly, the electric fields will push the electrons to explore ALL possible return paths, proportional to conductance (susceptance, for AC signals).

Yes, some paths will be preferred because of having lower impedance. But some electrons will still take other paths, because those other paths exist.

At frequencies well above SkinFrequency (5MHz for 35 micron 1-ounce/foot^2), the electrons do not have time to penetrate the foil, and (mostly) remain on one side. At 20MHz, you have 2 SkinDepths, or 2*8.9dB = 18dB of reduction (nearly 10:1). At 80MHz, you have 4 SkinDepths, or 4*8.9dB = 36dB of reduction (nearly 180:1). At 320MHz (perhaps 1nanosecond edges), you have 8 SkinDepths or 8*8.9dB = 72dB of reduction (over 30,000:1).

Note there STILL IS MOVEMENT of electrons thru the foil, to the side facing away from you aggressor trace. There still is I*R drop in that "quiet" side of the plane.

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