Short answer:
Assuming “regular CMOS” IO driver structure, the value of the output resistance can be estimated indirectly. Most of the DS provide data for “DC IO characteristics” from which you can calculate this parameter. Most of the time following is given:
a) Supply voltage (Vcc)
b) Load current (Iload)
c) Voltage drop @ load current (Vdrop)
The static resistance is straight forward Vdrop/Iload.
For example, PIC24F on table 26-10 for Vcc=2 V and Vdrop=0.4 V manufacturer specifies Iload=3.5 mA (worst case). This gives ~114 ohms. Note that increasing supply voltage to 3.6 V will increase Iload to 6.5 mA at the same voltage drop giving ~62 ohms.
Long answer:
I. First of all one need to check if in fact is dealing with “regular CMOS IO structure” which should be similar to following:
Unfortunately, μC manufacturers rarely provide this info (it is provided if you are dealing with discrete gates — such as 74HC family). However, I would claim this is the most common structure and there are tell-tell signs if it is actually used (more on this later).
II. If the above is true, one cane observe that on resistance would be in fact “on resistance” of the NMOS. In this case the VGS would be equal to supply voltage, VDS the Vdrop voltage and ID the Iload current.
Now what is left is to establish if data provided in manufacturer DS are from linear region or from saturation region. If data from DS Are from linear region, the “static resistance” calculated in very first point is pretty good approximation and be also valid for much smaller current. If the data are from the saturation region, the calculated resistance will be too pessimistic for smaller currents.
Above is illustrated by this characteristics from Wikipedia. Also, the whole article on MOSFETs is worth checking.
When VGS > Vth and VDS < VGS - VTH, the transistor is in linear region. It is pretty safe assumption that for CMOS technologies in which uC are manufactured the Vth is anywhere between 0.5–1.5 volts. So taking into account previous PIC24F example one can conclude with good probability that NMOS is in linear region ⇾ VGS (2V) > VTH (~1.5 V) and VDS (0.4) < VGS(2 V)-VTH(1.5V ).
Note: the MOS device even in so-called “linear region” is non-linear one. So quality of approximating it with a linear device (resistor) will depend on the point where the approximation was taken (operating point). In the examples above approximation is taken at pretty large current so it will be not very accurate at very low currents (actually it sets upper boundary for resistance).
III. So what are tell-tell signs that you are dealing with regular CMOS IO circuitry?
a) If you are lucky — there will be equivalent output stage schematic in DS
b) If you are lucky — as in case of MSP430G2231 on page 20 one will find Vdrop versus iload characteristics that is awfully similar to NMOS ID versus VDS characteristic. And as a plus from this characteristic, one directly get “static resistance” and tell if data provided by manufacturer are from linear or saturation region.
c) In other case, one can bet this is a case. Your odds for correct bet rise if ones' data show that driving current rises significantly with rising supply voltage.
