Studying for an exam Looking at Data buses using Wired AND and Wired OR configurations.

Using tristate logic, a device is able to gain control of the bus and transmit anything down it.

I don't understand Wired AND or Wired OR. The way I understand Wired AND at the moment - no device has control of the Bus and the output stays at a constant voltage (say 5V) if no devices are attempting to use the bus. However when a device attempts to use the bus the line will be pulled to 0V. Now if any device attempts to use the bus at the same time, it will never be clear which device is transmitting.

Also Wired AND is supposed to be active high however when a device uses the bus the line goes low. I would have thought this was active low.


"However when a device attempts to use the bus the line will be pulled to 0V."
That's it exactly: the bus is high only if all devices set it high. Just like in an AND gate the output is high only if all inputs are high.

Tri-state logic is not the way to control the bus; if one device sets it high, and another sets it low, you have a short circuit. Usually there's a passive pullup, which keeps the bus at its high level. Each device controls an open drain FET to pull it low.
Like you said, in this setup there's no way to determine how many devices are pulling it low simultaneously.

This is indeed active high logic: for the AND function the bus is active (high) if all inputs are active (high). If a device pulls the bus low it's just putting a low level on it.


In a common usage case for a wired-AND/wired-OR bus, there exists some means other than the bus by which devices can indicate whether they want attention. If there are five devices which may require attention but a processor has a single interrupt pin, a common solution would be to have the interrupt pin trigger some code that will ask each device in turn if it wants attention (and if so, service it). If the pin is still driven low after all devices have been polled, the polling cycle will repeat (in case a device which didn't want attention when it was first polled decides it wants attention while a later device is being serviced).

In general, a wired-AND/wired-OR bus will be used when there will often be zero devices wanting attention, and when it is useful to optimize for that case. It would be possible to forgo interrupts and simply have code repeatedly query every I/O device to see if it wants attention even when none do, but it is often far more useful to have code doing other things when no devices need attention.

BTW, another approach for using a bus that's electrically configured for wired-AND/wired-OR operation is to have devices only drive the line when explicitly addressed and asked to do so. Despite the electrical similarity, though, such configurations are often not referred to as wired-AND/wired-OR buses, since there's no possibility (when things are working as expected) of combining signals from unknown sources.

  • \$\begingroup\$ As an example, the Slave Select line of SPI devices is often used to explicitly address devices that are sharing a common SPI bus. \$\endgroup\$ – ajs410 May 16 '11 at 18:51
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    \$\begingroup\$ @ajs410: SPI with a shared data return would be an example of multiple devices sharing a common wire, but only talking on it when addressed. I think most SPI devices use 3-state outputs, precluding wire-or behavior, but since they're in the category of bus that would generally not be called wired-AND/wired-OR, that doesn't really matter. \$\endgroup\$ – supercat May 16 '11 at 18:59

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