Which synthesis tools support VHDL libraries?

Question

On various places across the net, I read that (some) synthesis tools do not respect VHDL libraries. These tools just throw all entities and packages into a single namespace, so that you cannot have mylib.someEntity and yourLib.someEntity in the same project. I know that Altera Quartus used to have that problem last time I checked (but that was a while ago). I'm afraid that some of the info on usenet archives might be outdated, so I'm looking for up-to-date info.

I also believe most simulators support libraries today.

My question: Which synthesis tools do support VHDL libraries and which don't? If there are any simulators that do not support libraries, I'd also like to hear that.

Can you please also mention the version numbers of the tools, for future reference?

Answer 1

I use the following tools which all have full library support:

• Riviera-PRO (from at least version 2006.02 onwards)
• Xilinx ISE (from at least version 10 onwards)
• Quartus (from at least version 10.0 onwards; Two or more entities with the same name cannot be used, however, only packages)
• Synplify (from at least version 9.0 onwards)

The only caveat is that the XST tool in the Xilinx toolchain is incapable of performing automatic file ordering on projects where entity names exist in multiple libraries (it ungraciously gets stuck looping forever trying to resolve dependencies).

Answer 2

Quartus uses a single library by default, but different libraries can be used if required:

http://quartushelp.altera.com/9.1/mergedProjects/hdl/vhdl/vhdl_pro_libraries.htm

Two or more entities with the same name cannot be used, however, only packages.

Answer 3

Synplify E2010.09-SP1-1 is OK: you can tell it what library to compile each file into in the project file

Sample code follows for others to try (not my normal coding style, I'd normally not use positional mapping, but in this simple situation it looked a bit cleaner).

The gate-view shows two LUTs one with an AND and one with an XOR.

lib1.vhd

library ieee;
use ieee.std_logic_1164.all;
entity test is
    port (a, b : in  std_logic;
          o    : out std_logic);
end entity test;
architecture a1 of test is
begin
    o <= a and b;
end architecture a1;

lib2.vhd

library ieee;
use ieee.std_logic_1164.all;
entity test is
    port (
        c, d : in  std_logic;
        o    : out std_logic);
end entity test;
architecture a1 of test is
begin
    o <= c xor d;
end architecture a1;

top.vhd

library ieee;
use ieee.std_logic_1164.all;

library lib1;
library lib2;

entity top is
    port (
        a, b, c, d : in std_logic;
        o1, o2     : out std_logic);
end entity top;

architecture a1 of top is
begin  -- architecture a1
    test_1: entity lib1.test port map (a, b, o1);
    test_2: entity lib2.test port map (c, d, o2);
end architecture a1;