Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data register?

Computer A we have 1K of words that are 16 bits each. Computer B is 16K of words with 32 bits each.

My understanding is that DR, AC, IR, TR are simply the size of a word. So they are 16 bits for computer A and 32 bits each in Computer B But AR and PC depend on the width of a memory address. How do you determine a memory address from the 16K x 32 memory information?

• The smallest size AR and PC could be is the number of bits required to address every word in memory; for A, there are 1024 addresses, and for B there are 16K addresses. Dec 11, 2014 at 6:39
• Note that it is usually more common to address at byte (8 bit) boundaries. If this is the case for your computers, compute the number of bytes in memory and this is the number of possible addresses your AR/PC need to be able to represent. Dec 11, 2014 at 6:41
• So, with computer A at 1024, it would be 10 bits for AR PC because 2^10 = 1024? And for Computer B it is 14 bits because 2^14 = 16,384? Dec 11, 2014 at 8:13
• You didn't read helloworld922's second comment about byte addressing. Try again. Dec 11, 2014 at 8:55
• So it has to align at both 16? Dec 11, 2014 at 23:12

You can't tell for sure just by looking at the size of the memory. Often the processor will have an addressing range that exceeds the amount of memory the computer is designed to take. Most processors have at least a 64k address range, so a computer with only 1k or 16k of memory is probably limited by other factors.

At the other end of the scale, having a large amount of memory does not mean that the processor must have equally large address registers. For example the Intel 8086 achieved a 1 Megabyte address range by adding two 16 bit registers together. Another way to increase addressing range is to use an I/O port to set the upper address lines, thus switching different bits of memory in one bank at a time (this is commonly used with 8 bit CPUs to access more than 64k of memory).

The size of data and instruction registers may match the data bus width, but there are many exceptions. 16 and 32 bit processors often have 8 bit registers that can be used independently or concatenated to make 16 or 32 bits. Some are able to access single bytes on a 16 or 32 bit data bus. It is also possible to have internal registers that are wider than the buses. For example the Motorola MC68008 executes 16 bit instructions and has 32 bit data and address registers, but only has an 8 bit data bus and a 20 bit address bus.

This sounds like a homework question based on a gross simplification of reality. So unfortunately to answer correctly requires knowing what simplifications of reality your instructors are making.

To address a memory with n locations requires ceil(log2(n)) address lines. For 1024 locations that means 10 address bits. For 16K locations that means 14 address bits.

Most practical systems using 16 or 32 bit wide memories allow addressing bytes within a word individually. So that would increase your address width for the 1024x16 system to 11 bits and your 16K*32 system to 16 bits. Whether the highly simplified systems your instructor is talking about do is another matter.

The address register and program counter need to be at least big enough to store a memory address but in reality they are likely to be wider. Again you need to know what assumptions your instructor is making.

Similarly the data registers are likely to be the same width as the memory data bus but are sometimes wider.