I always hear about process size improvements in the news, but could never figure out how it translates into dimensions of a logic gate. I found a chapter from Weste's CMOS VLSI Design, that contains figures which looks like things I create when playing KOHCTPYKTOP. There's a figure of a 3-input NAND gate, but none for a simple 2-input NAND. So I used Inkscape to draw my own, based on Mead & Conway's design rules mentioned in the chapter:

CMOS Fabrication design of NAND Gate

(I have no idea about the spacing around the well tap, I made it just 1 lambda)

So if I were to just plug in the current state of the art process size, which is supposedly 14 nm in 2014, can I say that the size of a NAND gate is about 448×518 nm²? Or is it possible to design it even smaller?


You can use that as a raw approximation. If you want to get better (or even get an idea of how much you are wrong), you better find someone who has access to a library or the design rules themselves and may speak about it (NDA are everywhere at that level).

Design rules for lower feature size are not a simple linear down scaling of the previous one. And new constraints are added which may make simple width and spacing adjustment just not enough. Mead & Conway is just a far too old source to even get an idea of the rules which apply for a state of the art process. For instance, I'd worry about the jog in poly, keeping strictly on routing direction was once for router convenience, and thus ignored in standard cell routing; nowadays, processes more or less mandate that as well, at least for some layers (and low level one such as diffusions and poly are the first to get the constraints).

Two remarks about your layout:

  • I'd not worry about the top spacing on the well, standard cells are often "vertically" mirrored (so the well of two adjacent rows are abutted, sometimes sharing the power rail).

  • I'd worry about how to route some signal to the poly. You'll want to drop vias on them, and thus the minimum spacing for poly may not be enough.

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