Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down network. Every implementation I've seen uses 6 transistors, with the output of a NOR circuit used as the input to an inverter circuit.
EDIT Added diagram created with Logisim. The boxes represent input pins, and the circle is an output pin. My knowledge of electronics is very limited, so I'm sorry I can't produce a detailed schematic. I'm a CS guy.