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Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down network. Every implementation I've seen uses 6 transistors, with the output of a NOR circuit used as the input to an inverter circuit.

EDIT Added diagram created with Logisim. The boxes represent input pins, and the circle is an output pin. My knowledge of electronics is very limited, so I'm sorry I can't produce a detailed schematic. I'm a CS guy.

OR Gate?

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  • \$\begingroup\$ Try drawing a schematic (for our benefit too since it's hard to visualize what you describe), and work through the different states to see what you get. \$\endgroup\$ – Majenko Dec 13 '14 at 22:18
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    \$\begingroup\$ That's because it's a really bad idea to use N-channel FETs as pullups and P-channel FETs as pulldowns. Every basic gate in CMOS has its output inverted. \$\endgroup\$ – Dave Tweed Dec 13 '14 at 22:54
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No. OR requires 6 transistors. NOR can be implemented with 4.

You can't put NMOS on top in a simple digital circuit because there is no voltage available to turn it on.

You can put NMOS on top on a linear analog circuit, but you will not be able to drive to the upper rail, unless there is some higher voltage available to drive the gate. If you need to drive all the way to the upper rail, you need PMOS on top.

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  • \$\begingroup\$ Yes, assuming it is a simple circuit with one VDD and one GND. If you are designing an IC, and there are multiple VCC rails, or charge pumps and such, maybe it could be done. I am not an expert. But not in a simple jellybean logic gate. \$\endgroup\$ – mkeith Dec 14 '14 at 21:17
  • \$\begingroup\$ Was editing my comment and took too long. Putting it back: Can't the 2 circuit inputs connected to the gates of the NMOS transistors supply the necessary voltage to turn them on? It sounds like NMOS can only be used to pull to ground for a digital circuit. \$\endgroup\$ – MarkZ Dec 14 '14 at 21:23
  • \$\begingroup\$ So from you've said and what @Majenko said in a linked response, VGS for the N-FETs would have to be too high to be practical since the N-FET source is connected to VDD? Excuse my likely misuse of terminology. \$\endgroup\$ – MarkZ Dec 14 '14 at 22:01
  • \$\begingroup\$ The threshold voltage, Vgs(th) would be positive for any NFET. So, ASSUMING THE INPUT IS AT VDD, as the output rose from 0 toward VDD, the current flowing through the transistor would become less and less until Vout = VDD - Vgs(th). This could kind of sort of work for a single gate in isolation, but if you tried to put two in series, the weak high output of the first gate would cause the second gate to output VDD - 2 * Vgs(th). And it would get worse for each sequential gate in the chain. So, it is no good. ;-) \$\endgroup\$ – mkeith Dec 14 '14 at 22:36
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What you have to consider is the gate-source voltage needed to turn on the FET. For example, when an input is high, you want the corresponding N-FET to pull the output to VDD. But if you factor in the gate-source on-voltage requirement, it does not work as needed.

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