I wonder if microcontrollers normally have cache or not.

What is the common case?

If not, what could be the benefit behind this?


2 Answers 2


Some do, some don't.

Low-end MCUs don't as a general rule. The reason for this is they're pretty simplistic devices with no pipeline or other optimizations. Just a simple 8-bit CPU core connected to address and data buses (usually Harvard architecture). They don't generally run fast enough to get any speed increase from cache as they can read from Flash at pretty much full speed anyway.

Higher end ones, typically most 32-bit ones, such as ARM and PIC32, do have cache. These usually run considerably faster (80MHz as opposed to 16MHz for instance) than little 8-bit MCUs, and as a result they can't read the Flash fast enough, so they have a small amount of cache, and a (usually 5-stage) pipeline, to make the whole system smoother and faster.


Generally not but the cortex-m4's do, I struggle to call them a microcontroller with both I and D caching, a floating point unit, etc. Microcontrollers generally rely on on-chip flash which is speed limited, some microcontroller families have plls for clock multiplication, but the flash may not be capable if the fastest speed the logic can handle, so you have to add more wait states, effectively speed limiting your fetching to the flash rate (some have prefetch features to help that). So I caching can help there. D caching doesnt make much sense, but it could also be that the faster you go the more expensive sram is, but I dont remember having to mess with wait states on the sram, so D caching doesnt necessarily make sense, you have to be careful with D caching anyway without an mmu or some other way to isolate register space from general ram. Some core designs are such that there is a boundary where the peripherals must be and the ram must be and so an mmu is not required to tell you where cachable regions are you can simply turn on the d cache if you have one.

The short answer is the same reason you would use a cache on any other processor. To separate a faster processor from its slower, cheaper, memory. Keep it at least for bursts from being memory bound.


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