One of the questions in my textbook (Introduction to Computing Systems) asks to design a 3-input AND gate. The given solution is as follows:
If I am reading this correctly, this is a 3-NAND–NOT combination. I don't understand why you need the NAND–NOT instead of just creating an AND by itself. My proposed schematic is the following:
This seems simpler, and uses fewer transistors, so I'm guessing that there's some reason that it won't work (otherwise it would be the example solution!).
I don't see any possibilities for short-circuiting: if
NOT OUT, so there will be no path from power to ground (because it would have to go through
On the other hand, I do think that everything is properly grounded: if
OUT should have a path to ground through whichever of
(A,B,C) is logically false.
What am I missing?