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One of the questions in my textbook (Introduction to Computing Systems) asks to design a 3-input AND gate. The given solution is as follows:

Given 3-AND gate solution

schematic

simulate this circuit – Schematic created using CircuitLab

If I am reading this correctly, this is a 3-NAND–NOT combination. I don't understand why you need the NAND–NOT instead of just creating an AND by itself. My proposed schematic is the following:

My proposed 3-AND gate

schematic

simulate this circuit

This seems simpler, and uses fewer transistors, so I'm guessing that there's some reason that it won't work (otherwise it would be the example solution!). I don't see any possibilities for short-circuiting: if NAND(A,B,C), then NOT OUT, so there will be no path from power to ground (because it would have to go through OUT). On the other hand, I do think that everything is properly grounded: if NAND(A,B,C), then OUT should have a path to ground through whichever of (A,B,C) is logically false.

What am I missing?

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  • \$\begingroup\$ I'm not quite sure how to use the schematic editor. If someone wants to replace my images, please feel free! \$\endgroup\$ – wchargin Dec 14 '14 at 17:55
  • \$\begingroup\$ You're missing how MOSFETs work and what the gate voltage (Vgs) has to be. \$\endgroup\$ – Majenko Dec 14 '14 at 17:59
  • \$\begingroup\$ Related: electronics.stackexchange.com/questions/143811/… \$\endgroup\$ – Ignacio Vazquez-Abrams Dec 14 '14 at 18:04
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The problem here is that you're misunderstanding (or not having the basic understanding) of how MOSFETs work, in particular the \$V_{GS}\$.

On an N-channel MOSFET the gate voltage has to rise a certain amount above the source pin. On a P-channel it has to fall a certain amount below the source pin.

In your schematic the N-channel's source is connected to \$V_{CC}\$ and the P-channel's to GND. If the threshold is, say, 1.2V (a reasonable logic level threshold), then the input logic HIGH would have to be at least 1.2V above \$V_{CC}\$ and the logic LOW would have to be below -1.2V.

That, as you can see, just isn't practical.

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  • \$\begingroup\$ You're certainly right that I don't understand how these work :) Is $V_{CC}$ just the battery/power voltage? (The bar at the top of my hand-drawn schematic?) And what is $V_{GS}$? \$\endgroup\$ – wchargin Dec 14 '14 at 18:13
  • \$\begingroup\$ Hmm...so is the key that the gate voltage is compared relative to the source voltage, as opposed to, say, \$0\,\mathrm{V}\$? In that case, would it ever make sense to connect an N-type transistor to power or a P-type transistor to ground? \$\endgroup\$ – wchargin Dec 14 '14 at 18:30
  • \$\begingroup\$ There are times when you would do that, but you generally require a special driving circuit. In normal logic it's never used like that. \$\endgroup\$ – Majenko Dec 14 '14 at 19:10
  • \$\begingroup\$ \$V_{GS}\$ is the difference in voltage between the gate and the source pins. \$V_{CC}\$ is the supply voltage (battery voltage). \$\endgroup\$ – Majenko Dec 14 '14 at 19:11
  • \$\begingroup\$ Thanks very much for your help! You've certainly given me some things to think about. \$\endgroup\$ – wchargin Dec 14 '14 at 22:14

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