How does this voltage detector IC work in a circuit? What does open drain vs. CMOS output mean?

Question

I'm evaluating the Rohm BD48/BD49 series voltage detector. I'm having trouble understanding the data sheet.

I want to generate a high signal when the input voltage is above a desired threshold (3.0 volts, so the BD4xx30x), and low when it's below that. This chip comes in two varieties, one of which is an "open drain" and the other is "CMOS". The data sheet says:

For both the open drain type ... and the CMOS output type ... When the voltage applied to the VDD pins reaches the appropriate threshold voltage, the VOUT terminal voltage switches from either “High” to “Low” or from “Low” to “High”.

I think that means high-to-low, or low-to-high respectively? I.E. A) the open drain type when input voltage is below the threshold generates a high signal on the output pin (but as mentioned elsewhere, only via an external pullup), which goes low when input voltage exceeds the threshold, while B) the CMOS type generates a low signal when the input voltage is below the threshold, which switches high when the input voltage exceeds the threshold.

So I think that I want the BD49 CMOS series, with its Vout hooked straight to the control pin (active high) of the chip I want to pair it with. Is that right? I'm guessing based mostly on some assumptions of the accompanying figures.

Answer 1

To answer your question, both ICs (the open-drain and the "CMOS" types) have the same output characteristics: they will pull the output high when the input voltage is high, and pull the output low when the input voltage is low. See the Output vs Input voltage graphs on pg. 9 (Fig 6). In short, either IC will work for your purpose, but the open-drain one will require an external pull-up resistor (whether or not the open-drain or the "CMOS" type is more useful for you depends on your application).

The datasheet mentions "low to high" and "high to low" separately, I believe, in order to imply that there is hysteresis on the output (and indeed, the rest of that sentence refers to a different part of the datasheet discussing the IC's built-in hysteresis). Hysteresis is a feature that essentially means you have two separate threshold voltages, depending on the type of change occurring. For instance, the low-to-high threshold voltage will be higher than the high-to-low threshold, to avoid rapid switching (bouncing) of the output when there is noise in the input.

Ignacio covered the difference between open-drain and the "CMOS" output, so I won't go into that here.

Answer 2

An open drain output refers to an output stage where the pull-up transistor is missing. This means that rather than outputting a high voltage when the output is high, it presents a high impedance to the circuit and an external pull-up resistor is used to provide the high voltage. This is useful when there is more than one device that wants to output to the same line; since none of the devices can pull the line high, there is no way to create a high-to-low short circuit.

A CMOS output generally refers to a normal push-pull output where the low voltage is no more than 0.1V_DD and the high output is no less than 0.9V_DD.

Answer 3

No I think it's telling you when the voltage exceeds a threshold the output will go from low to high. This would make a good microprocessor reset for example. It would only release reset when the voltage was above a certain level.

Then it will monitor the voltage and if it goes below a threshold then it's output will go from high to low. This is good for brownout protection. If your vcc drops below the operational threshold of your chip you want it to reset.

There is some hysteresis around the thresholds so the thing doesn't oscillate wildly in the transition region.

Open drain is a common way to do reset so someone else, the uc itself or another device can pull the line low.