Apologies for this vague title, but my question is a little specific.

I have two concerns :

During my digital electronics class, I was told that the design of the processor is first carried on an FPGA board and verified. Only then it is finalized. In order to design the processors on FPGA board, you use Verilog and VHDL, and then let the tools do the heavy lifting. These tools then infer or deduce a schematic / design from our program. Also, simultaneously, another team of engineers is busy programming test benches and carry out verification and simulation etc.

My first question :

If you let the tools do the designing portion of your processor (or microprocessor), 
then wont it always infer the same circuit, or at least nearly same circuit 
for your processor ?

For example, as one of lab exercises, we were required to program a 4 bit ALU on xilinx ISE in verilog. As long as we had the same instructions / operations/ functionality for our ALU , if we let the tools design ALU, wont it always design the same circuit ? I believe this because ultimately at the transistor level, an AND gate (just an example )will always be composed of, lets say 5 mos transistors (as provided in the library of components ). Also ALU will always contain same blocks / nearly same blocks like adder, subtractor etc ( In other words, same design will be inferred).

My second question :

If I am correct above ( which obviously I doubt ), then how would the designs differ ? 
In other words, where lies the role of a human / engineer if everything is 
done by the tools .

As another example, Intel produces processors. If we for the time being assume that they produce on 28 nm, and will continue to do so for another 5 years ( just an example) . Then how is it that they come up with fast processors every year or so ? I am confused because at the end of the day, Intel itself will obviously be using these kind of tools (verilog / vhdl) to design their chips. So as long as they have a functionality which does not change, they should always come up with same design.

Please understand that this is not a broad question. It focus on the automation aspects / designing using tools only. Also I am not concerned with advances in computer science concepts, such as introduction of pipelines etc which improved performance. I am only interested in above mention aspects.

I am asking this because I am little interested in designing a small microprocessor before my graduation. But programming a couple of lines in Verilog / vhdl and letting the tools do the job does not seem to excite me at all.

Thank you.

  • \$\begingroup\$ I actually had a similar experience in college. We spent an entire quarter building an entire 4 bit uProcessor from the gate level up. We'd put the gates together, create the pin-outs and then black-box it up and move on to the next level up. In the next class in the series, we spent 1 week creating that same processor in verilog which ended up being 16 lines of code. Although it was fun the first time building things from gates up, you would rapidly find it to be tedious. There's so much more potential to do more interesting and sophisticated projects with these tools. \$\endgroup\$ – horta Dec 15 '14 at 15:17
  • \$\begingroup\$ @horta. I am kinda familiar with the power of tools ( designed a simple ALU in couple of lines as mentioned in Q). But I am not able to understand where does the scope of improvement in design lies ( and thus excitement) if we remove "reducing size of components" and computer science concepts from the equation, and talk only in terms of using tools to design. You and akellyirl kind of touched that thing ( "We design the ALU and then incorporate it in tool") but its still a little unclear. \$\endgroup\$ – Plutonium smuggler Dec 15 '14 at 15:29
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    \$\begingroup\$ Is perhaps the problem that you've only seen trivially simple problems for the tool you're working with? Also, I think of pipelines, interconnects, and caches as computer engineering concepts rather than computer science concepts. Those really are the next steps in making a processor faster besides increasing clock speed and performing more in a single cycle. Another important aspect of computer engineering in the last 5ish years has been power management which allows the chip to work more efficiently rather than just faster. \$\endgroup\$ – horta Dec 15 '14 at 15:43
  • \$\begingroup\$ @horta.Could be. So far, only worked on simple problems like 'design a shift register' or 'design an adder, alu etc'. Can you cite some real problems ( sources would be great). Maybe that could help. (Also, I think what akellyirl is saying is somewhat similar to gate level modelling ?) \$\endgroup\$ – Plutonium smuggler Dec 15 '14 at 15:46
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    \$\begingroup\$ Ahaha, yeah sorry, the first step would obviously be to build a single core. If you're only building a 4 bit processor, it won't be too difficult. You can expand the problem space in any direction you want though. Making a pipelined processor, and then adding power management features to shut off parts of the pipeline when not in use would also require some design work on your part. How deep your pipeline would be is up to you; which stages would shut off when is up to you. In the "real world", multiple core interconnection has evolved greatly. In short, lotsa problems that tools don't solve. \$\endgroup\$ – horta Dec 15 '14 at 16:17

If you let the tools do the designing portion of your processor (or microprocessor), then wont it always infer the same circuit, or at least nearly same circuit for your processor ?

No. There are several low-level details which will result in different circuitry. Suppose you design an adder. You are really only designing the functional specification of the adder, either in high level terms (e.g. verilog "+" operator) or lower level terms such as gates. However this design must be mapped onto the actual blocks or gates which will implement the design. On an FPGA you may have a macro-cell or a look-up table (LUT) structure which gets repeated in an array across the chip. For an ASIC you have raw gates.

As part of this there is typically some kind of "place and route" step which will map the functional blocks onto the two dimensional layout of the resources on the FPGA or ASIC. Placing an routing are not simple algorithms - my understanding is that they are "NP complete" as there is not a polynomial time algorithm to find the optimum layout and routing. As a typical part of a design you will specify timing constraints to be met, and the place and route will try to operate so that these constraints are met. Because the process is not exhaustive (it would take too much time) a "seed" value is typically used to determine how to start out, and then a solution is looked for that is close to where it needs to be. Different seeds will produce different layouts with the same functional characteristics but (usually slightly) different timings.

If I am correct above ( which obviously I doubt ), then how would the designs differ ? In other words, where lies the role of a human / engineer if everything is done by the tools .

As other answers have mentioned, the actual functional design is not done by the tools. But there is still room for human interaction with the tools in determining the actual functioning. In addition to specifying timing requirements it is sometimes necessary to go back and tweak the design to accomodate these requirements. For instance, the tools might identify a critical path which limits the clock frequency at which the design can run. This might be slower than is desired, and the engineering would need to go back and figure out how to make it meet timing, such as pipelining, reducing fan-out, and so forth.


I think you're misunderstanding the "design" that the tools do when you say "let the tools do the designing portion of your processor".

In general design progresses from a top-level spec to

  1. Architecture,
  2. Design
  3. Implementation

The tools are very useful at all stages for simulation and modelling but really come into their own during implementation.

For example: the diagram below shows a top-level block for an ARM processor (source).

enter image description here

Once you have your top-level spec, you then need to design the architecture. You might model it and simulate it in Verilog or C++ or your favourite high-level language and arrive at something like this where you have added ALU, shifter etc.. to implement the required functions of the specifications: enter image description here

Then at the design level you will design individual blocks in RTL Verilog (for example).

Once this simulates OK. You can use the tools to implement the design. Typically this means Synthesis from RTL to Cell-Library, Placement of the Cells, Routing of the cells, parasitic extraction, timing analysis etc.

The tools do a lot of the heavy lifting at the implementation stage but they do not do the design.

Several years ago there were tools to take Architectural level designs and synthesise them into RTL but they are not mainstream tools.

It should be said that companies provide configurable processors as IP in their synthesis flow. For example, Synopsys Designware ARC processor Cores, where the IP only needs to be configured in your SOC design.

  • \$\begingroup\$ Do you mean to say that WE design this ALU part ( with hand), include our design in this software and let the tool do the simulation part ? So the tool is only good for simulation and verification, not designing ? \$\endgroup\$ – Plutonium smuggler Dec 15 '14 at 14:50
  • \$\begingroup\$ Yes. The tools will turn you design at Register Transfer Level (RTL) into logic gates (more correctly, standard cells). Take a look at the (source) link in my answer. I think you'll find it useful. \$\endgroup\$ – akellyirl Dec 15 '14 at 14:55
  • \$\begingroup\$ I still dont understand properly. Continuing with the ALU example , an ALU I believe will always contain functionality like add, sub, shift, and , or etc. So how can one come upon a different ALU design with same functionality ; be it tool or human ? \$\endgroup\$ – Plutonium smuggler Dec 15 '14 at 14:58
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    \$\begingroup\$ @Plutoniumsmuggler Many ALU's are different. Some have a built in multiplier, some have square root capabilities, some are for floating point vs integer. Even then, two equivalent ALU's one can be implemented to be faster with more gates or slower with fewer gates (generally speaking). \$\endgroup\$ – horta Dec 15 '14 at 15:02
  • \$\begingroup\$ @Plutoniumsmuggler Any block only does what it's specified to do in the architecture stage. ALU is not a defined function like a NOR gate is. An ALU my be pipelined, have an output register, contain status outputs, all kinds of things that make it different to another ALU. \$\endgroup\$ – akellyirl Dec 15 '14 at 15:02

If you take out all the complicated things like pipelines, then no it's not particularly complicated and you can do a reasonable 8 bit cpu in a few hundred lines of Verilog.

The pipelining, branch prediction, prefetch, cache etc is what gives designers the speed increases, and what consumes the development effort and chip area.

(Chip tapeout isn't entirely automated in the same way as software compilation, so going from Verilog to silicon involves quite a bit of configuring and hinting the tools to achieve good results at 28nm. Especially timing closure.)

Edit: have a browse of OpenCores OpenRisc design where you can get a feel for how much Verilog is required for a fully useful modern design.

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    \$\begingroup\$ I recall designing an 4 bit MIPS processor out of a few more than 16 lines of code back in college. The power of the tools is amazing really. \$\endgroup\$ – horta Dec 15 '14 at 14:59

The tools convert a functional specification into a physical implementation. And yes, if the specification doesn't change, then the implementation won't either.

The "human engineering" part of it is coming up with the functional specification in the first place. Different processors have different functionality, and are sometimes designed to have special features to support a particular class of applications.

Even when the basic architecture is well-defined (such as Intel x86), there are still variations in low-level details, such as speciallized instructions, and there are other options within the chip with regard to the number of cores, how they're interconnected, the number and the sizes of caches, etc.

  • \$\begingroup\$ I have yet to find a tool that converts "a functional specification into a physical implementation" (except for Powerpoint of course). \$\endgroup\$ – akellyirl Dec 15 '14 at 14:53

There are also custom circuit designers who break blocks out of synthesis and design them at the transistor/gate level. This is typically done for the critical paths.


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