I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right

When doing the following shift for the Denom the new MSB of the numerator to compare with is the old MSB-1 Therefore I have implemented a Down counter that starts with M downto 0 at each step the new MSB is the value read from the counter

on VHDL Implementation I got an error on the following


the obtained error is: type identifier with "ctr_reg" does not agree with its usage as "natural type"

How can I solve this? should be done with a variable inside my process? And what is the hardware translation of a variable used in such case

Thank you

Included Libraries

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.classic_multiplier_parameters.all;

Error From updated statement:

if(numerator(to_integer(unsigned(ctr_reg)))='1') then

altera error

  • \$\begingroup\$ Can you post the definitions of numerator and ctr_reg? What type are they? \$\endgroup\$
    – Paebbels
    Dec 15, 2014 at 19:03
  • \$\begingroup\$ They are of std_logic_vector, I have added the following statement , 'variable index:natural:=M'; and 'index:=index-1'; I am not getting any error but i do not know how variables work, is it sequentially ? and does it create a sub-tractor ? \$\endgroup\$
    – chaosmind
    Dec 15, 2014 at 19:04
  • \$\begingroup\$ std_logic_vector: This infers that you are using the package 'std_logic_(un)signed' instead of 'numeric_std'. std_logic_vector is not a good type for counters and vectors used for arithmetic computations. \$\endgroup\$
    – Paebbels
    Dec 15, 2014 at 19:21
  • \$\begingroup\$ The error says that: delete one of the library that has unsigned decleration. Then try to convert ctr_reg to natural number with the functions of the existing library. \$\endgroup\$
    – electro103
    Dec 15, 2014 at 20:28

1 Answer 1


I assume that ctr_reg is of type (un)signed because it's a counter.

VHDL expect normal indices to be of type integer (natural, positive are subtypes of integer). See the definition for std_logic_vector:

type STD_LOGIC_VECTOR is array (NATURAL range <>) of STD_LOGIC;

So you must convert your counter from (un)signed to integer:

if (numerator(to_integer(ctr_reg)) = '1') then

If ctr_reg is of type std_logic_vector (slv), then you must also convert slv to unsigned:

if (numerator(to_integer(unsigned(ctr_reg))) = '1') then

If this construct is to long, write a function (let's say to_index(..)) which hides these conversions :)

if (numerator(to_index(ctr_reg)) = '1') then

A definition for to_index(..) can be found here.

Edit 1:

List of commonly used packages in VHDL:

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;  -- common std_logic(_vector) operations
use     IEEE.NUMERIC_STD.ALL;     -- defines signed and unsigned and their operations
  • \$\begingroup\$ I have added a screenshot of the obtained error after changing the statement to, if (numerator(to_integer(unsigned(ctr_reg))) = '1') then, i have also included the numeric library...ctr_reg: std_logic_vector(L-1 downto 0); and L is defined as constant L: integer := 4; \$\endgroup\$
    – chaosmind
    Dec 15, 2014 at 19:36
  • \$\begingroup\$ Please add your changes and VHDL lines to your original question. The formatting of source code is much better and other reads can follow the conversation more easily. Can you write your complete list of library and use statement? \$\endgroup\$
    – Paebbels
    Dec 15, 2014 at 20:58
  • \$\begingroup\$ Updated, and I have removed the use ieee.std_logic_unsigned.all; Thank you \$\endgroup\$
    – chaosmind
    Dec 15, 2014 at 21:00
  • \$\begingroup\$ Thanks :) Please, also remove use ieee.std_logic_arith.all; and use ieee.std_logic_unsigned.all;. All the needed types and functions are provided by the newer package numeric_std ;) \$\endgroup\$
    – Paebbels
    Dec 15, 2014 at 21:04
  • \$\begingroup\$ ok Great Thank you :D what do you recommend as VHDL learning Ebook? \$\endgroup\$
    – chaosmind
    Dec 15, 2014 at 21:10

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