I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named
a_o in my circuit) as flag to show that the maximum number of the counter has been reached.
The circuit is working fine, but it is inferring a Flip-Flop in the
a_o signal that I don't want to be there. I have checked all reasons why an unexpected flip-flop can appear but I still can't solve the problem.
Many thanks in advance
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ej11 is generic (N : positive := 4; M : positive := 10); port ( e_i : in std_logic; nmr_i : in std_logic; clk_i : in std_logic; a_o : out std_logic; q_o : out std_logic_vector (N-1 downto 0)); end entity ej11; architecture Comportamiento of ej11 is signal aux : unsigned (N-1 downto 0); signal acarreo : std_logic; begin Cuenta: process (clk_i, nmr_i) begin if nmr_i='0' then aux <= (others => '0'); acarreo <= '0'; elsif rising_edge (clk_i) then if e_i = '1' then if aux < M-1 then aux <= aux + 1; else aux <= (others => '0'); end if; if aux = M-2 then acarreo <= '1'; else acarreo <= '0'; end if; end if; end if; end process Cuenta; q_o <= std_logic_vector (aux); a_o <= acarreo; end architecture Comportamiento;