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I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the maximum number of the counter has been reached. The circuit is working fine, but it is inferring a Flip-Flop in the a_o signal that I don't want to be there. I have checked all reasons why an unexpected flip-flop can appear but I still can't solve the problem.

Many thanks in advance

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ej11 is 

    generic (N : positive := 4;
                M : positive := 10);
    port (
            e_i :   in std_logic;
            nmr_i : in std_logic;
            clk_i   :   in std_logic;
            a_o :   out std_logic;
            q_o :   out std_logic_vector (N-1 downto 0));
end entity ej11;

architecture Comportamiento of ej11 is

    signal aux  :   unsigned (N-1 downto 0);
    signal acarreo : std_logic;

begin
    Cuenta:
    process (clk_i, nmr_i)
    begin
        if nmr_i='0' then
            aux <= (others => '0');
            acarreo <= '0';
        elsif rising_edge (clk_i) then
            if e_i = '1' then
                if aux < M-1 then
                    aux <= aux + 1;
                else
                    aux <= (others => '0');
                end if;

                if aux = M-2 then
                    acarreo <= '1';
                else
                    acarreo <= '0';
                end if;
            end if;
        end if;
    end process Cuenta;
    q_o <= std_logic_vector (aux);
    a_o <= acarreo;
end architecture Comportamiento;
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Remove the carry from the process (it's declaration is also unneeded unless accarreo is read in another process or concurrent statement ):

architecture Comportamiento of ej11 is

    signal aux  :   unsigned (N-1 downto 0);
    -- signal acarreo : std_logic;

begin
    Cuenta:
    process (clk_i, nmr_i)
    begin
        if nmr_i='0' then
            aux <= (others => '0');
            -- acarreo <= '0';
        elsif rising_edge (clk_i) then
            if e_i = '1' then
                if aux < M-1 then
                    aux <= aux + 1;
                else
                    aux <= (others => '0');
                end if;

                -- if aux = M-2 then
                --    acarreo <= '1';
                -- else
                --    acarreo <= '0';
                -- end if;
            end if;
        end if;
    end process Cuenta;
    q_o <= std_logic_vector (aux);
    -- a_o <= acarreo;
end architecture Comportamiento;

Either add a concurrent assignment or a new process with an assignment to a_o (conditional concurrent assignment shown):

    a_o <= '1' when aux = M-2 else
           '0';

Including the assignment to accareo inside the if statement is inferring sequential logic inferred the flip flop.

A process would look something like:

Acarreo:
    process (aux)
    begin
        if aux = M-2 then
            a_o <= '1';
        else
            a_o <= '0';
        end if;
    end process Acarreo;
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Does it help if you add an else condition corresponding to the if e_i = '1' then line?

It looks like acarreo (and aux) are not assigned if e_i is 0. I suppose the flip-flop is associated with a_0 because it is essentially just a buffered version of acarreo and they may be optimized to a single signal.

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  • \$\begingroup\$ That might work. e_i is an enable signal, if it's '0' the counter shouldn't modify its value even on a rising edge. How can I write that down? a_o <= a_o doesnt seems logic. \$\endgroup\$ – cventu Dec 15 '14 at 19:49
  • \$\begingroup\$ I didnt work. I put acarreo and aux to zero when e_o is '0' but the Flip-Flop is still there \$\endgroup\$ – cventu Dec 15 '14 at 20:00

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