Am trying to code a top level module that would connect different modules to make an up/down counter that would display a hexadecimal character on a 7 segment LED on posedges; but every time I try to run the following top level module I get an error that says

'Line 25: Syntax error near "<=".'

There is no one else to ask this and am following the same outline of the example in my reference book. What am I doing wrong?

module Main_Module(a, b, c, d, e, f, g, U, R, P, Clk);
   input U, R, P, Clk;
   output a, b, c, d, e, f, g;
   reg [3:0] Data;
   wire In3 <= Data[3], In2 <= Data[2], In1 <= Data[1], In0 <= Data[0];  //This is Line 25

  Counter Counter_1(Clk_1Hz, R, P, U, Data);
  Segment_Display Segment_Display_1(a, b, c, d, e, f, g, In3, In2, In1, In0);
  ClkDiv1Hz ClkDiv1Hz_1(Clk, R, Clk_1Hz);


Thank you Eugene Sh.and Greg for your time!


2 Answers 2


Wires need blocking assignments (=), not non-blocking (<=). You can define it this way:

wire In3 = Data[3], In2 = Data[2], In1 = Data[1], In0 = Data[0];

Example here

More commonly you will see the declaration and assignments as separate statements. The two are functionally equivalent

wire In3, In2, In1, In0;
assign {In3, In2, In1, In0} = Data;
  • \$\begingroup\$ That Works! I always had this problem with assignments, though could get away with "<=" in all assignments I need. Do you know if that would effect flow of bits? Because I was told that non-blocking assignments are instant while the blocking assignments are slower \$\endgroup\$
    – ellis
    Commented Dec 17, 2014 at 21:22
  • 1
    \$\begingroup\$ Non-blocking is not slower, just updated in a later region in the scheduler. This is to prevent race conditions for flop to flop assignments. Generally flops (latches edge triggered flip-flops) should be assigned with non-blocking assignments, everything else should be blocking assignments. \$\endgroup\$
    – Greg
    Commented Dec 17, 2014 at 21:29

You are trying to declare and use the non-blocking assignment to a wire in the same line. Verilog does not allow using non-blocking assignments in this way. Either use the blocking assignment = or first declare the wires:

wire In3;
wire In2;
wire In1;
wire In0;

and then assign them somewhere:

In3 <= Data[3];
In2 <= Data[2];

or even better:

wire [3:0] In;
In <= Data; // Assuming your data is 4 bit
  • \$\begingroup\$ I tried the first way you suggested and I got few errors that said "In3 is an unknown type" "In2 is an unknown type""In1 is an unknown type" and "In0 is an unknown type" even though I already declared them as wires \$\endgroup\$
    – ellis
    Commented Dec 17, 2014 at 21:01
  • \$\begingroup\$ I couldn't use the easier method because the module "Segment_Display" have In3, In2, In1 and In0 rather that [3:0] In \$\endgroup\$
    – ellis
    Commented Dec 17, 2014 at 21:02
  • \$\begingroup\$ If you show the complete code, we will resolve it as well. \$\endgroup\$
    – Eugene Sh.
    Commented Dec 17, 2014 at 21:02
  • \$\begingroup\$ @user3465945 You can pass In[0], In[1],... to the module. \$\endgroup\$
    – Eugene Sh.
    Commented Dec 17, 2014 at 21:04
  • 1
    \$\begingroup\$ @EugeneSh. Wires can be declared and assigned in the same line. Multiple declarations & assignments is the same line are also allowed. They cannot be assigned with non-blocking assignments. \$\endgroup\$
    – Greg
    Commented Dec 17, 2014 at 21:16

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