# Verilog: Change a Certain Delay According to the Current Output

For Verilog 2005, when writing the test bench, is it possible to create a lookup table of delay values, and then assign a certain value in it to be the delay of some procedural block?

For example:

reg        clk;
reg  [9:0] delay [0:15]; //suppose delay[i] = 10'di;

always #delay[i]
begin
clk <= ~clk;
end


and I somehow change i to read out a certain delay value.

Moreover, is it possible to make a lookup table of delays with floating point values?

An array of 16 floating point elements: real delay [0:15];.

Within the always block, a wait statement is needed to allow the delay values to be populated. Because it is a clock, I suggest adding a condition checker to terminate the simulation if it fails. This safeguard is to catch 0-time infinite loops while the simulation is running.

reg clk;
integer i;
real delay [0:15];

always begin
wait( ^i !== 1'bx); // This gives us a change to populate delay
if (delay[i] <= 0.0 || i < 0 || i > 15) begin
$display("FATAL @ %0t :: Something gone honorably wrong. i:%0d range 0 to 15, delay[%0d]:%0f",$realtime,i,i,delay[i]);
$finish(1); end #(delay[i]); clk = ~clk; end  Working example Here delay[j] is a look up table of real values which can be varied in the expression "delay[i]=1.2+i". This real valued delay can be used as setting time period for a clock in always block as shown below. timescale 1ns/1ps module del; real delay[0:15]; integer i,j; reg clock; initial begin for(i=0;i<16;i=i+1) begin delay[i]=1.2+i; //can be any expression such that delay can be a real value end end initial begin$dumpfile("dump.vcd");
$dumpvars(1); clock=0; j=3; // Can be any integer #400$finish;
end

always begin
#delay[j] clock=~clock;
end
endmodule
`