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In this circuit from (Grey,Meyer Analysis and Design of Analog Integrated circuits fifth edition) It is stated that : "In the quiescent condition,\$ V_o = 0\$ and \$V_1 = 0\$ ." What forces V1 and Vo to be equal 0 when \$V_i =0\$ ?Aren't there other sources (\$V_{cc}, -V_{cc}\$) which may cause \$V1\$ to be >0 ?

edit :It is actually mentioned that this is a simplified schematic of the output stage of the 709 op amp

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    \$\begingroup\$ This is an incomplete circuit. The "quiescent condition" possibly implies external circumstances that make this condition happen : not shown in what we have here. Presumably these are not important to the point the writer is about to make... \$\endgroup\$
    – user16324
    Dec 18, 2014 at 14:12
  • \$\begingroup\$ It doesn't make sense, looking at this circuit if Vi = 0, Q3 is off, but V1 = +Vcc and Q1 is on, therefore V0 is not 0 either. There is probably something else going on that you are not showing. \$\endgroup\$
    – davidrojas
    Dec 18, 2014 at 14:33

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Brian is right. This is not a complete circuit. Do not bother attempting to analyze the quiescent conditions of this circuit.

For the record, as drawn, if \$V_i\$ is greater than 0.6V above \$-V_{CC}\$, then the collector of \$Q_3\$ will be near ground and \$Q_2\$ will pull the output voltage down toward \$-V_{CC}\$. Grey and Meyer are well-respected, but maybe write for an advanced audience. I am sure that when presented in full context, everything makes sense.

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The quoted text from the book is:

In the quiescent condition, \$V_o = 0\$ and \$V_1 = 0\$ .

This is correct in the sense that these are the conditions under which no current flows through the stage, and the output is at 0V.

This appears to be from you:

What forces \$V_1\$ and \$V_o\$ to be equal \$0\$ when \$V_i = 0\$?

The answer is nothing. The question's premise isn't true. The "quiescent condition", as described, requires \$V_i\$ to have some specific value which is neither 0 from ground, nor from \$-V_\text{CC}\$. It is that value which turns on \$Q_3\$ just enough so that exactly the right amount of current flows through \$R_1\$ to create the correct voltage drop for the conditions.

That value would arise, in the overall amplifier, thanks to feedback. When the overall amplifier (not shown) is configured with a feedback network, say for unity gain, an output of 0V would be ensured by tying the input to 0V. Internally, the right condition will arise in the \$Q_3\$ circuit.

But it will not be the case that \$V_i\$ is zero from any obvious reference point. The voltage will be somewhere in the neighborhood of \$Q_3\$'s \$V_\text{BE}\$ (above \$-V_\text{CC}\$), since that transistor has to be partially turned on and be in its active region: neither saturated, nor cut off.

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