I was reading something when I came across a project using the SN74180 parity checker IC. I begin looking at the datasheet when I came across this description:
The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level to facilitate the connection of unused inputs to used inputs. Typical power dissipation is 170 mW.
What is meant by a "normalized series load" and why would you need an input buffer?
It seems like this description is alluding to the fact that this device supports up to 10 fan-out loads for each output at logic LOW, and 20 at logic HIGH.
How can this number be different for each type of logic level?
It would seem that the fact that it can support 20 fan-out at logic HIGH would be moot since the 10 fan-out at LOW would be a bottle-neck anyway. Surely I am misunderstanding this characteristic.
What is meant by ".. facilitate the connection of unused inputs to used inputs"?