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I was reading something when I came across a project using the SN74180 parity checker IC. I begin looking at the datasheet when I came across this description:

The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level to facilitate the connection of unused inputs to used inputs. Typical power dissipation is 170 mW.

What is meant by a "normalized series load" and why would you need an input buffer?

It seems like this description is alluding to the fact that this device supports up to 10 fan-out loads for each output at logic LOW, and 20 at logic HIGH. 

How can this number be different for each type of logic level?

It would seem that the fact that it can support 20 fan-out at logic HIGH would be moot since the 10 fan-out at LOW would be a bottle-neck anyway. Surely I am misunderstanding this characteristic.

What is meant by ".. facilitate the connection of unused inputs to used inputs"?
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What is meant by a "normalized series load"

A digital input requires a certain amount of current in order to pull the input stage high or low enough to have a voltage within the logic thresholds. This amount of current is designated "1 normalized series load", and it varies per family.

and why would you need an input buffer?

Certain logic devices, e.g. muxes, have complex structures that consist of more than 1 load. The input buffer hides these extra loads.

How can this number be different for each type of logic level?

Both TTL inputs and TTL push-pull outputs are asymmetrical, but not balanced to each other. This results in a discrepancy in the load handling.

What is meant by ".. facilitate the connection of unused inputs to used inputs"?

This one I'm not sure about. Floating TTL inputs are seen as high regardless, so I'm not sure how this would come into play.

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  • \$\begingroup\$ On the last question- perhaps a recognition that connecting n NAND style TTL inputs together results in only one TTL load when low and n loads when high.. so if you have several inputs you can just connect them together (probably on adjacent pins) rather than using the recommended 1K pullup resistor to Vcc. Ancient history here- and confirmed that it says that in my old TTL data book. \$\endgroup\$
    – Spehro Pefhany
    Dec 21, 2014 at 22:05
  • \$\begingroup\$ @Ignacio, Regarding the third question you answered above, I was thinking more of how this could be done. That is, if you have this in a circuit, how can you have 10 fan-out loads and 20 fan-out loads (for low and high output levels, respectively)? \$\endgroup\$
    – sherrellbc
    Jan 16, 2015 at 14:43
  • \$\begingroup\$ @SpehroPefhany, I think I am missing the point. Do you literally mean to connect the output of a previous TTL load together directly and feed this into the input of another? \$\endgroup\$
    – sherrellbc
    Jan 16, 2015 at 14:44
  • \$\begingroup\$ @sherrellbc I mean that if you connect two inputs of an SN7400 NAND gate together you have two loads when high, but only one load when low. It doesn't say that anywhere that I've seen, but if you look at the schematic it has to be true. \$\endgroup\$
    – Spehro Pefhany
    Jan 16, 2015 at 14:53
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It's not a normalized series load, it's a normalized 7400-series load. They're talking about representative values for the current of a 7400-series input pin.

The fan-out can be different for different logic levels because TTL inputs consume different current at high and low levels, and the high-side and low-side output drivers are different. The datasheet shows that for the SN74180, high-level input current is less than 40 microamps, while low-level input current is less than 1.6 milliamps. The high-level output current is no more than 800 microamps, while the low-level output current can be up to 16 milliamps.

What I'm not clear on is how this helps with tying off unused inputs. I can see how connected unused inputs to used inputs would be easier from a board layout standpoint, but I don't know why the high-level current load would matter more.

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