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I am working on a circuit where I need to use different clock sources. I am using two HCMOS oscillators. Both oscillators have an disable pin. When disabled, the clock output buffer is placed in tri-state.

Can I safely connect both lock outputs with each other and use the disable pins so that only one oscillator is enabled at a time? The following image shows what I mean.

enter image description here

NOTE: Glitch-free switching between clock signals in not required.

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  • \$\begingroup\$ I would use a single-gate inverter such as a 74LVC1G14 to save a port pin and ensure that only one oscillator is enabled at a time. \$\endgroup\$ – Spehro Pefhany Dec 21 '14 at 20:49
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Your circuit concept will work just fine as long as you only enable one oscillator at a time. After all there are reasons that oscillators like these are equipped with an output enable/disable pin. Your application is one of the reasons.

Some food for though. To ensure that both oscillators are never enabled at the same time you need to properly comprehend how the two enable signals are generated. If the two signals come from a microcontroller (which I suspect is the case) you can easily control the enables via the software to ensure that at least one of the enables is low at any given time. However when the MCU is in reset or before the software is active you have to make sure that the default (reset) state of the enable circuitry abides by the only one active at a time rule. A good way to handle this can be to design so that both enables are low in the disabled state through power up and until the MCU software is active and able to select one or the other enable. An effective way to deal with this is to use MCU pins that default at powerup and out of reset as inputs to the MCU. You can then put suitable pulldowns on each of the enable lines to hold the lines low until software eventually comes along and configures the two pins as outputs and drives one high.

The job to ensure proper operation gets slightly more complicated if these oscillators are actually supplying the clocking signal to the MCU itself. (I suspect that this is not the case for your application since you said that glitchless switching was not required. It the MCU was fed from the clocking selector on the fly then you would need a glitchless design. You would also need to design the circuitry so that one enable was active and the other was disabled in the default (reset) state.

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  • \$\begingroup\$ Thanks for your answer, it has pointed me to the fact that I have forgotten to add pull-down resistors to the disable pins -- the output is enabled if the disable pin is floating. \$\endgroup\$ – sergej Dec 21 '14 at 18:54
  • \$\begingroup\$ @sergej - You are welcome. I think my answer touches on a lot of important considerations that the other answers do not even touch on. If you design things correctly there never should be an instance the two outputs are enabled at the same time except for some type of build failure at time of circuit manufacture. In addition the series resistors that you have on the outputs are placed there - and you may be aware of this already - to series back match the driver output impedance to the trace impedance on the circuit board. Trying to select and use these resistors as (continued) \$\endgroup\$ – Michael Karas Dec 21 '14 at 19:07
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    \$\begingroup\$ (continued from above) current limit resistors, as the other answers suggest, is not a correct approach. You need to maintain the flexibility to freely select the proper series matching resistor once you are on PC board to optimize signal integrity of the clock signals and not be constrained by current limit issues. \$\endgroup\$ – Michael Karas Dec 21 '14 at 19:12
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With the circuit as given, the oscillators have to be able to withstand 50mA if both become enabled for some reason. If this is within spec for them then it will work, otherwise you should either increase the resistances, use oscillators with higher tolerances, or put them behind a 2:1 mux.

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  • \$\begingroup\$ Thanks for your answer. The datasheet says: max output current=+/-24 mA. So I will try to increase the resistances to 68 Ohm. \$\endgroup\$ – sergej Dec 21 '14 at 17:52
  • \$\begingroup\$ @sergej: Assuming everything is perfect, with a 3.3V output from the oscillator and 24 mA through the 68 ohms in series with its output, there'll be 1.632 volts dropped across the resistor, which will leave 1.668 volts to drive the load. Everything won't be perfect, of course, So what are the tolerances on the outputs of your oscillators with various loads, the inputs to your loads, and what do your loads look like? \$\endgroup\$ – EM Fields Dec 21 '14 at 18:14
  • \$\begingroup\$ Although CMOS inputs won't draw anywhere near 24mA, of course. \$\endgroup\$ – Ignacio Vazquez-Abrams Dec 21 '14 at 18:15
  • \$\begingroup\$ @IgnacioVazquez-Abrams: Of course, but I don't recall reading that the inputs are CMOS. ;) \$\endgroup\$ – EM Fields Dec 21 '14 at 18:21
  • \$\begingroup\$ @EMFields: The oscillator supplies the master clock signal to two DACs. The load current is far below 1mA. \$\endgroup\$ – sergej Dec 21 '14 at 18:33
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Since tri-stating a logic output puts it in a condition where it appears to disappear from the bus, your scheme will work as long as MCLK1_EN and MCLK2_EN are mutually exclusive.

There's a caveat, though... make sure that the output capacitance of the disabled oscillator, during shutdown, isn't enough to load the enabled oscillator to the point where it can't clock the following stage/s.

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