The title is probably good enough, but I've always wondered why decoupling caps aren't built into the chip or at least the IC packaging?
Integrating capacitors on a chip is expensive (they need a lot of space) and not very efficient (you're limited to extremely small capacitors).
The packaging doesn't offer the room neither, the capacitor would be in the way of the bonding.
IC package miniaturization is driven by the cellphone market (hundreds of megadevices a year, if not a gigadevice). We always want smaller packages, both in area and in height. Just open your cellphone to see what the problem is. (My phone is 1 cm thin, which includes housing top and bottom, a display, a 5 mm thick battery, and between that there's a PCB with components.) You can find BGA packages less than a mm high (this SRAM package is 0.55 mm(!)). That's less than the height of a 0402 100 nF decoupling capacitor.
Also typical of SRAM is that package size isn't standard. You find 8 mm * 6 mm, but also 9 mm * 6 mm. That's because the package fits the die as closely as possible. Just the die plus on each side a fraction of a mm for the bonding. (BTW, BGA dies are bonded on an integrated PCB, which routes the signals from the edges to the ball grid.)
This is an extreme example, but other packages like TQFP don't leave much more room.
It's also much cheaper to pick and place a capacitor on the PCB; you're doing this anyway for the other components.
Oversimplified, one could say: *Capacitor designers don't like to use advanced 45 nm processing, and IC designers have little to no idea about how to get an extremely big \$\epsilon_r\$ out of barium titanate.*
The materials used in chips are optimized for semiconductors, not for things needed in capacitors (i.e. extremely high dielectric constants). And even if they were, on-chip capacitors would still use a lot of space, making the chips very expensive. The relatively large area for an on-chip capacitor would have to go through all the tricky process steps needed for the original chip functionality. Therefore, the only capacitors built onto the chip structure are those that can be very small anyway or those that are required to be trimmed very precisely to what the IC is intended to to, e.g. the charge redistribution capacitors of a successive-approximation analog-to-digital converter that must even be trimmed while the chip is still being manufactured.
For things like decoupling of the chip's supply rails or buffering its reference node, where the precise value of the capacitor doesn't matter too much but where a high C*V product is needed, it is way better to place some capacitors next to the ICs. These can be made of electrolytic or ceramic material trimmed for much capacitance*voltage in a small volume, and fabricated in a process ideal for these requirements.
Then, there are of course some hybrid packaging techniques where ceramic capacitors are placed onto or into the same package with an IC, but these are exceptions where either the length of the connectors from the die through a standard IC package and socket to a cap on the board would already be too long and have too much inductance, or where the IC manufacturer doesn't want to rely on the board designers to actually read their data sheets and application notes about where the caps must be placed so the IC can meet its specifications.
If the question is why decoupling cap's aren't encapsulated along with the die in the packaging, I would say that the main reason is economics -- in most cases, there's not much of a performance gain to bring the capacitor on-board (instead of having it on the PCB) - so the extra cost (in process development, testing, and cost of goods) brings no benefit to the consumer and just adds to the cost of the device.
The existing packaging processes would have to be modified to accomodate the in-package chip, too. That would add significant amount of costs for new or modification of existing tooling (machines, molds, inspection equipment, and on and on) --- just to add that extra capacitor.
As for placing capacitors directly on the die -- that die space is more valuable as transistors than as capacitors. Again, for the capacitance, you're better off with it outside of the core die packaging.
I don't buy this. MAX3233E has 4, FOUR, 0.1uf charge pump caps built in the package, yet needs a 5th decoupling cap of the same exact 0.1uf rating on the outside.
Smallest package for that part is large (for today), SOIC-20, and the chip is collossally expensive, $9 in single quantities, which explains why every chip doesn't do that, but it does not explain why there are 4 caps built in and yet the thing still requires a 5th of the exact same cap externally.
Also, however much bigger a cap will make a package, the final result of that larger package with no external cap, must be smaller than the normal package with external cap.
Perhaps the real reason is because board/circuit designers need the freedom to decide how much and what form the decoupling shall take. Maybe one application needs 3 different size caps to cover a wide frequency range, maybe another application gets away with no decoupling at all, maybe another application the decoupling cap actually introduces a problem they couldn't address if it were built in and irremovable.