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The title is probably good enough, but I've always wondered why decoupling caps aren't built into the chip or at least the IC packaging?

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    \$\begingroup\$ They sometimes are! I've seen PC CPUs with them. It's too expensive for ordinary devices, and will make them too large. \$\endgroup\$ – Leon Heller May 20 '11 at 13:14
  • \$\begingroup\$ As people have mentioned you can get the caps built in to the socket. I found these on RS other suppliers may sell them as well. Although they are more expensive then just standard sockets. I feel that the cost might not be worth it in industry compared with buying the sockets and caps separately. \$\endgroup\$ – Dean May 21 '11 at 8:22
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    \$\begingroup\$ @Leon: That could be an answer instead of a comment :) \$\endgroup\$ – endolith May 23 '11 at 14:02
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    \$\begingroup\$ @endolith - it was an answer! don't make it too difficult for Leon. :-) \$\endgroup\$ – stevenvh Jun 9 '11 at 15:49
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Integrating capacitors on a chip is expensive (they need a lot of space) and not very efficient (you're limited to extremely small capacitors).
The packaging doesn't offer the room neither, the capacitor would be in the way of the bonding.

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IC package miniaturization is driven by the cellphone market (hundreds of megadevices a year, if not a gigadevice). We always want smaller packages, both in area and in height. Just open your cellphone to see what the problem is. (My phone is 1 cm thin, which includes housing top and bottom, a display, a 5 mm thick battery, and between that there's a PCB with components.) You can find BGA packages less than a mm high (this SRAM package is 0.55 mm(!)). That's less than the height of a 0402 100 nF decoupling capacitor.
Also typical of SRAM is that package size isn't standard. You find 8 mm * 6 mm, but also 9 mm * 6 mm. That's because the package fits the die as closely as possible. Just the die plus on each side a fraction of a mm for the bonding. (BTW, BGA dies are bonded on an integrated PCB, which routes the signals from the edges to the ball grid.)
This is an extreme example, but other packages like TQFP don't leave much more room.

It's also much cheaper to pick and place a capacitor on the PCB; you're doing this anyway for the other components.

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  • \$\begingroup\$ it would be nice to have some references, but a nicety, not required. \$\endgroup\$ – Kortuk May 20 '11 at 19:19
  • \$\begingroup\$ Would it be possible, on some chip packages, to have concave areas molded into the underside of the package where capacitors could be placed on board? That wouldn't work on chips where the package and die are nearly the same size, but on many packaged ICs the die cavity is a small portion of the package. \$\endgroup\$ – supercat May 20 '11 at 19:26
  • \$\begingroup\$ @Kortuk - typically Kortuk, always wanting more! :-) The thing is that manufacturers don't make statements why they don't integrate decoupling capacitors; for them it's obvious. \$\endgroup\$ – stevenvh May 21 '11 at 10:16
  • \$\begingroup\$ I'm sorry, but I don't buy "it's obvious..." because I think that's a narrow view that doesn't look at the big picture. I agree about the cell phone and packaging concerns, that's probably true. It's seems to me that a material that has the desired capacitance could be designed into the packaging and just bonded to by the wire bonder. Maybe that's not obvious or perhaps more likely ignorant. Not to mention, I would think they require more space on the board than integrated in any way. \$\endgroup\$ – kenny May 21 '11 at 11:47
  • \$\begingroup\$ @kenny - I said it's obvious for the manufacturer, not that it should be for us mere mortals. And about an external cap requiring more space: that's only true if they don't have to enlarge the package to fit the capacitor in. And like I explained in the BGA example, there's simply no room to place an 0402, probably not even an 0201. Besides, the latter don't go to 100 nF. (I'm also wondering if the bonding machine doesn't require a flat surface.) \$\endgroup\$ – stevenvh May 21 '11 at 14:16
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Oversimplified, one could say: *Capacitor designers don't like to use advanced 45 nm processing, and IC designers have little to no idea about how to get an extremely big \$\epsilon_r\$ out of barium titanate.*

The materials used in chips are optimized for semiconductors, not for things needed in capacitors (i.e. extremely high dielectric constants). And even if they were, on-chip capacitors would still use a lot of space, making the chips very expensive. The relatively large area for an on-chip capacitor would have to go through all the tricky process steps needed for the original chip functionality. Therefore, the only capacitors built onto the chip structure are those that can be very small anyway or those that are required to be trimmed very precisely to what the IC is intended to to, e.g. the charge redistribution capacitors of a successive-approximation analog-to-digital converter that must even be trimmed while the chip is still being manufactured.

For things like decoupling of the chip's supply rails or buffering its reference node, where the precise value of the capacitor doesn't matter too much but where a high C*V product is needed, it is way better to place some capacitors next to the ICs. These can be made of electrolytic or ceramic material trimmed for much capacitance*voltage in a small volume, and fabricated in a process ideal for these requirements.

Then, there are of course some hybrid packaging techniques where ceramic capacitors are placed onto or into the same package with an IC, but these are exceptions where either the length of the connectors from the die through a standard IC package and socket to a cap on the board would already be too long and have too much inductance, or where the IC manufacturer doesn't want to rely on the board designers to actually read their data sheets and application notes about where the caps must be placed so the IC can meet its specifications.

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  • \$\begingroup\$ Thanks for that info, very helpful. I was actually more thinking it of package integrated as in your last paragraph. Seems to be that the lead frame venders, sorry if that's dated, could it into the design. Maybe something about that process or the expense to do it is why? \$\endgroup\$ – kenny May 21 '11 at 11:39
  • \$\begingroup\$ AFAIK, capacitors are soldered in hybrid packages, and hybrid packages always contain some sort of board material, be it ceramic or similar to FR4 (but with a thermal extension characteristic that better matches silicon). With only a die, a leadframe and a package around that, there is bonding only, and no soldering. I don't know if caps can actually be bonded. \$\endgroup\$ – zebonaut May 21 '11 at 16:31
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There used to be IC sockets with decoupling capacitors built in. Haven't seen them in years, tho

enter image description here

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    \$\begingroup\$ can you provide examples or links to examples of these old IC sockets? \$\endgroup\$ – Jeff Atwood May 21 '11 at 6:29
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    \$\begingroup\$ The question was about caps within ICs (die) or IC packages. This is an IC socket, not a package. These sockets may have been invented to save space on PCBs while SMT was not yet the norm, and they are limited to common logic packages where GND is on pin (#total_pins/2) and VCC is on pin (#total_pins) \$\endgroup\$ – zebonaut May 21 '11 at 8:29
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    \$\begingroup\$ @Jeff - I added an image to lyndon's answer. The reason why you don't see those anymore is that they apply only to a specific pinning, like Vcc on pin 20, gnd on pin 10. Typically LSTTL and HCMOS building blocks. Placing power pins like that was a pretty daft idea to start with, and it's not done anymore. Modern ICs can have their power pins pretty much anywhere, but they're often placed more closely together. Also, this is DIL!, who uses that anymore? :-) \$\endgroup\$ – stevenvh May 21 '11 at 8:29
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    \$\begingroup\$ @stevenvh, I know it's in jest, but... we still use DIL, a lot! :( When designing with high power, it's lowest cost my EE power supply partner tells me because many components require thru-hole and thus it's more expensive to have both in the board fab. \$\endgroup\$ – kenny May 21 '11 at 11:42
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    \$\begingroup\$ when I first saw this I thought it was a Photoshop joke \$\endgroup\$ – Joel B Jun 8 '11 at 16:59
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If the question is why decoupling cap's aren't encapsulated along with the die in the packaging, I would say that the main reason is economics -- in most cases, there's not much of a performance gain to bring the capacitor on-board (instead of having it on the PCB) - so the extra cost (in process development, testing, and cost of goods) brings no benefit to the consumer and just adds to the cost of the device.

The existing packaging processes would have to be modified to accomodate the in-package chip, too. That would add significant amount of costs for new or modification of existing tooling (machines, molds, inspection equipment, and on and on) --- just to add that extra capacitor.

As for placing capacitors directly on the die -- that die space is more valuable as transistors than as capacitors. Again, for the capacitance, you're better off with it outside of the core die packaging.

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  • \$\begingroup\$ @whoever downvoted this - It would be nice if you let us know why you did. It may allow @Toybuilder to improve his answer. \$\endgroup\$ – stevenvh Jun 8 '11 at 15:21
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    \$\begingroup\$ I don't see anything here that deserves a down vote. It's not a great answer in that it doesn't add that much new or goes into much detail, but it's not wrong, inappropriate, insulting, or otherwise evil either. I just gave it one up vote to bring it back to 0. Normally I wouldn't have voted this up, but I thought leaving it negative was unfair. \$\endgroup\$ – Olin Lathrop Jun 8 '11 at 15:39

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